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  • 3 bit comparator

    From =?UTF-8?B?RMawxqFuZyBExrDGoW5n?=@21:1/5 to All on Sun Mar 28 08:25:28 2021
    comparator3bit.vhd:library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity comparator3bit is
    port (
    p : in std_logic_vector(2 downto 0);
    q : in std_logic_vector(2 downto 0);
    p_le_q : out std_logic
    );
    end comparator3bit;

    Architecture Behavior of comparator3bit is
    begin
    process (p, q)
    begin
    if p<q then p_le_q <= '1';
    else p_le_q <= '0';
    end if;
    end process;
    end Behavior;

    comparator3bit_tb.vhd:
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;

    entity comparator3bit_tb is
    end comparator3bit_tb;

    Architecture tb of comparator3bit_tb is
    component comparator3bit_tb is
    port ( p : in std_logic_vector(2 downto 0);
    q : in std_logic_vector(2 downto 0);
    p_le_q : out std_logic);
    end component;
    signal p,q : std_logic_vector(2 downto 0) := (others => '0');
    signal p_le_q : std_logic;
    signal i,j : integer;
    begin
    UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q => p_le_q);
    process
    begin
    for i in 0 to 8 loop
    p <= std_logic_vector(to_unsigned(i+2,3));
    q <= std_logic_vector(to_unsigned(i,3));
    end loop;
    wait;
    end process;
    end;

    When I run the simulation comparator3bit_tb and add the wave then the graph does not show p_le_q output. How to fix thanks

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  • From Maurice SAAB@21:1/5 to Maurice SAAB on Mon Mar 29 09:58:49 2021
    On 29/03/2021 09:57, Maurice SAAB wrote:
    On 28/03/2021 18:25, Dương Dương wrote:
    comparator3bit.vhd:library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity comparator3bit is
        port (
            p : in std_logic_vector(2 downto 0);
            q : in std_logic_vector(2 downto 0);
            p_le_q : out std_logic
            );
    end comparator3bit;

    Architecture Behavior of comparator3bit is
    begin
        process (p, q)
        begin
        if p<q then p_le_q <= '1';
        else p_le_q <= '0';
        end if;
        end process;
    end Behavior;

    comparator3bit_tb.vhd:
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;

    entity comparator3bit_tb is
    end comparator3bit_tb;

    Architecture tb of comparator3bit_tb is
        component comparator3bit_tb is
        port ( p : in std_logic_vector(2 downto 0);
            q : in std_logic_vector(2 downto 0);
            p_le_q : out std_logic);
        end component;
        signal p,q : std_logic_vector(2 downto 0) := (others => '0');
        signal p_le_q : std_logic;
        signal i,j : integer;
    begin
        UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q
    p_le_q);
        process
        begin
        for i in 0 to 8 loop
            p <= std_logic_vector(to_unsigned(i+2,3));
            q <= std_logic_vector(to_unsigned(i,3));
             end loop;
        wait;
        end process;
    end;

    When I run the simulation comparator3bit_tb and add the wave then the
    graph does not show p_le_q output. How to fix thanks

    you should wait for some time after assigning p and q, try this:
    for i in 0 to 8 loop
            for i in 0 to 8 loop
            p <= std_logic_vector(to_unsigned(i+2,3));
            q <= std_logic_vector(to_unsigned(i,3));
           end loop;
        wait;
    HTH





    you should wait for some time after assigning p and q, try this:
    for i in 0 to 8 loop
    for i in 0 to 8 loop
    p <= std_logic_vector(to_unsigned(i+2,3));
    q <= std_logic_vector(to_unsigned(i,3));
    wait for 100 ns;
    end loop;
    wait;
    HTH




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  • From Maurice SAAB@21:1/5 to All on Mon Mar 29 09:57:28 2021
    On 28/03/2021 18:25, Dương Dương wrote:
    comparator3bit.vhd:library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity comparator3bit is
    port (
    p : in std_logic_vector(2 downto 0);
    q : in std_logic_vector(2 downto 0);
    p_le_q : out std_logic
    );
    end comparator3bit;

    Architecture Behavior of comparator3bit is
    begin
    process (p, q)
    begin
    if p<q then p_le_q <= '1';
    else p_le_q <= '0';
    end if;
    end process;
    end Behavior;

    comparator3bit_tb.vhd:
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;

    entity comparator3bit_tb is
    end comparator3bit_tb;

    Architecture tb of comparator3bit_tb is
    component comparator3bit_tb is
    port ( p : in std_logic_vector(2 downto 0);
    q : in std_logic_vector(2 downto 0);
    p_le_q : out std_logic);
    end component;
    signal p,q : std_logic_vector(2 downto 0) := (others => '0');
    signal p_le_q : std_logic;
    signal i,j : integer;
    begin
    UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q => p_le_q);
    process
    begin
    for i in 0 to 8 loop
    p <= std_logic_vector(to_unsigned(i+2,3));
    q <= std_logic_vector(to_unsigned(i,3));
    end loop;
    wait;
    end process;
    end;

    When I run the simulation comparator3bit_tb and add the wave then the graph does not show p_le_q output. How to fix thanks

    you should wait for some time after assigning p and q, try this:
    for i in 0 to 8 loop
    for i in 0 to 8 loop
    p <= std_logic_vector(to_unsigned(i+2,3));
    q <= std_logic_vector(to_unsigned(i,3));
    end loop;
    wait;
    HTH





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  • From Charles Bailey@21:1/5 to All on Thu Apr 1 21:33:59 2021
    On 2021-03-28 10:25, Dương Dương wrote:
    comparator3bit.vhd:library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity comparator3bit is
    port (
    p : in std_logic_vector(2 downto 0);
    q : in std_logic_vector(2 downto 0);
    p_le_q : out std_logic
    );
    end comparator3bit;

    Architecture Behavior of comparator3bit is
    begin
    process (p, q)
    begin
    if p<q then p_le_q <= '1';
    else p_le_q <= '0';
    end if;
    end process;
    end Behavior;

    comparator3bit_tb.vhd:
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;

    entity comparator3bit_tb is
    end comparator3bit_tb;

    Architecture tb of comparator3bit_tb is
    component comparator3bit_tb is
    port ( p : in std_logic_vector(2 downto 0);
    q : in std_logic_vector(2 downto 0);
    p_le_q : out std_logic);
    end component;
    signal p,q : std_logic_vector(2 downto 0) := (others => '0');
    signal p_le_q : std_logic;
    signal i,j : integer;
    begin
    UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q => p_le_q);
    process
    begin
    for i in 0 to 8 loop
    p <= std_logic_vector(to_unsigned(i+2,3));
    q <= std_logic_vector(to_unsigned(i,3));
    end loop;
    wait;
    end process;
    end;

    When I run the simulation comparator3bit_tb and add the wave then the graph does not show p_le_q output. How to fix thanks


    Main problem: your FOR loop doesn't advance simulation time with each iteration. Your whole simulation completes in 0 ps. Put a WAIT
    statement, such as "wait for 20 ns;" before the "end loop;"

    A few other comments:
    Remove the references to the std_logic_arith and std_logic_unsigned
    packages. Those are non-standard packages that came from Synopsys, not
    IEEE, and are considered deprecated. Plus, you are not actually using
    them anyway.

    Because your testbench uses entity instantiation for comparator3bit, you
    don't need the component definition for it.

    Charles Bailey

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