mitchalsup@aol.com (MitchAlsup1) writes:
Maybe now with 4-or-5-bit condition codes yes,
But the early machines (360) with 2-bit codes were already constricted.
The B3500 (contemporaneous with 360) had COMS toggles (2 bits) and OVERFLOW toggle (1 bit).
In their archtecture book Brooks and Blaauw say it was a mistake, but
it also would have been a problem to fit conditional branches into the >instruction set if they needed more instruction bits to say which
codes to test. As it was, the branch instructions had 4 condition bits
which let them check for any combination of two-bit conditions along
with 1111 for unconditional branch and 0000 for no-op.
John Levine <johnl@taugh.com> writes:
[only 2 condition code bits]
The architecture paid for the reduction in branches with an increase
in other instructions; S/360 needed signed and unsigned versions of a
number of instructions, e.g.,
signed unsigned
A AL
AR ALR
S SL
SR SLR
C CL
CR CLR
IBM then continued in their tradition by having < = > and sticky
overflow flags in Power (and a separate carry, sticky overflow and
overflow flag); this also requires signed and unsigned compares (cmp
and cmpl along with variants).
John Levine <johnl@taugh.com> writes:
[only 2 condition code bits]
In their archtecture book Brooks and Blaauw say it was a mistake, but
it also would have been a problem to fit conditional branches into the >>instruction set if they needed more instruction bits to say which
codes to test. As it was, the branch instructions had 4 condition bits >>which let them check for any combination of two-bit conditions along
with 1111 for unconditional branch and 0000 for no-op.
The architecture paid for the reduction in branches with an increase
in other instructions; S/360 needed signed and unsigned versions of a
number of instructions, e.g.,
signed unsigned
A AL
AR ALR
S SL
SR SLR
C CL
CR CLR
Other instruction sets with 16-bit instructions have no problem
supporting the usual NCZV flags.
IBM then continued in their tradition by having < = > and sticky
overflow flags in Power (and a separate carry, sticky overflow and
overflow flag); this also requires signed and unsigned compares (cmp
and cmpl along with variants).
- anton
It is my impression that
trapping on fixed point overflow is not very useful, and it's easier
to do a jump on overflow in the few cases where you care, or the x86
INTO which you put after the arithmetic operaion to trap if the
overflow flag is set.
John Levine <johnl@taugh.com> schrieb:
It is my impression that
trapping on fixed point overflow is not very useful, and it's easier
to do a jump on overflow in the few cases where you care, or the x86
INTO which you put after the arithmetic operaion to trap if the
overflow flag is set.
Sanitzers would benefit greatly from trapping math.
However, this could get into murky territory - to be really
general, you would also need a version for trapping math with
unsigned numbers. Just think of doing a unsigned loop with a
lower bound that, due to some error in the code or input, has an
upper bound of 0-1...
According to Thomas Koenig <tkoenig@netcologne.de>:
John Levine <johnl@taugh.com> schrieb:
It is my impression that
trapping on fixed point overflow is not very useful, and it's easier
to do a jump on overflow in the few cases where you care, or the x86
INTO which you put after the arithmetic operaion to trap if the
overflow flag is set.
Sanitzers would benefit greatly from trapping math.
However, this could get into murky territory - to be really
general, you would also need a version for trapping math with
unsigned numbers. Just think of doing a unsigned loop with a
lower bound that, due to some error in the code or input, has an
upper bound of 0-1...
I suppose but my experience was always that the trap was the easy
part.
Figuring out what to do after the trap happens is much harder.
I've seen designs with instructions like "trap if greater than N" so
if you want to go that route, you can check for the range the
programemr declared rather than whatever word size it was rounded up
to.
(*) x86 takes craploads of cycles to cross the trap barrier and back {including the saving and restoration of registers}
Something like My 66000 takes 10 each way including the saving and
restoring of registers, and the change of MMU state.
MitchAlsup1 <mitchalsup@aol.com> schrieb:
(*) x86 takes craploads of cycles to cross the trap barrier and back
{including the saving and restoration of registers}
Something like My 66000 takes 10 each way including the saving and
restoring of registers, and the change of MMU state.
(Maybe) stupid question: What happens to in-flight instructions on
such a trap, or an interrupt? What is the cost of that?
Just think of doing a unsigned loop with a lower bound that, due to some error in the code or input, has an upper bound of 0-1...
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