The CPU books I have do not cover a test/debug interface for the processor, so I am winging it a bit.
On 5/4/25 9:40 PM, Robert Finch wrote:
The CPU books I have do not cover a test/debug interface for the processor, so I am winging it a bit.
The ones I have seen are based on scan chains, going back to the "muffler" in the Xerox Dorado
Even state-of-the-art CPUs today commonly use scan-chains (via JTAG)
for debuggin.
Even state-of-the-art CPUs today commonly use scan-chains (via JTAG)
for debuggin.
Is there some blog somewhere that explains how scan-chains work (not
how they're used, but how they're implemented inside the CPU)?
Intuitively they sound very costly to me, because of things like the
need to run extra wires all over the place. I'm obviously
missing something.
Even state-of-the-art CPUs today commonly use scan-chains (via JTAG)
for debuggin.
Is there some blog somewhere that explains how scan-chains work (not
how they're used, but how they're implemented inside the CPU)?
Intuitively they sound very costly to me, because of things like the
need to run extra wires all over the place. I'm obviously
missing something.
Stefan
In the distant path, I had the select lines (the heavy loads that
cross the data path and select things for it to do) captured at
the other end of the data path with a skewable scan clock so we
could (essentially) see the timing of the select lines after
crossing the data path. This made it possible to use the scan
path as an oscilloscope.
Actually, you're not far off. It's a serial shift chain which is shifted one-bit at a time to capture flop states. Each chain is a single wire;Even state-of-the-art CPUs today commonly use scan-chains (via JTAG)Is there some blog somewhere that explains how scan-chains work (not
for debuggin.
how they're used, but how they're implemented inside the CPU)?
Intuitively they sound very costly to me, because of things like the
need to run extra wires all over the place. I'm obviously
missing something.
a chip may have a few dozen individual shift chains. https://www.design-reuse.com/articles/48331/scan-chains-pnr-outlook.html
What's the approximate cost of those scan chains. I.e. if we were to
take an existing working design and replace all the "flip-flop with scan-chain" with "plain flip-flops", how much smaller would the
resulting chip be, how much faster could it run, and how much less power could it consume?
On 5/6/25 8:12 PM, Stefan Monnier wrote:
What's the approximate cost of those scan chains. I.e. if we were toI wouldn't matter because it wouldn't be testable in production.
take an existing working design and replace all the "flip-flop with
scan-chain" with "plain flip-flops", how much smaller would the
resulting chip be, how much faster could it run, and how much less power
could it consume?
Actually, you're not far off. It's a serial shift chain which isEven state-of-the-art CPUs today commonly use scan-chains (via JTAG)Is there some blog somewhere that explains how scan-chains work (not
for debuggin.
how they're used, but how they're implemented inside the CPU)? >>>Intuitively they sound very costly to me, because of things like the
need to run extra wires all over the place. I'm obviously
missing something.
shifted
one-bit at a time to capture flop states. Each chain is a single wire;
a chip may have a few dozen individual shift chains.
https://www.design-reuse.com/articles/48331/scan-chains-pnr-outlook.html
Thanks. Wow. So it is really that bad, huh?
I also liked the note about speed limits and power consumption, how
shifting a state (in or out) causes (almost) all the flip-flops to
change state at each cycle, thus leading to very high power consumption.
What's the approximate cost of those scan chains. I.e. if we were to
take an existing working design and replace all the "flip-flop with scan-chain" with "plain flip-flops", how much smaller would the
resulting chip be, how much faster could it run, and how much less power could it consume?
I assume the cost in terms of power consumption is small because in
normal use, the scan-chain part stays completely stable so that barring leakage it should not consume any power, save for the indirect costs
like the need to move the other bits over greater distances when
the extra wires of the scan chains get in the way.
Stefan
MitchAlsup1 wrote:
In the distant path, I had the select lines (the heavy loads that
cross the data path and select things for it to do) captured at
the other end of the data path with a skewable scan clock so we
could (essentially) see the timing of the select lines after
crossing the data path. This made it possible to use the scan
path as an oscilloscope.
Was that the AMD with the 6 phase clock you mentioned before?
I was wondering about how boundary scan would work with that.
I suppose you'd have 6 separate scan paths to capture each
phases logic states.
What's the approximate cost of those scan chains. I.e. if we were toGiven a 16-gate delay design with 5 gates of "flop-jitter-skew"
take an existing working design and replace all the "flip-flop with
scan-chain" with "plain flip-flops", how much smaller would the
resulting chip be, how much faster could it run, and how much less power
could it consume?
the scan path adds about ½ a gate of delay (2%-ish).
What's the approximate cost of those scan chains. I.e. if we were toGiven a 16-gate delay design with 5 gates of "flop-jitter-skew"
take an existing working design and replace all the "flip-flop with
scan-chain" with "plain flip-flops", how much smaller would the
resulting chip be, how much faster could it run, and how much less power >>> could it consume?
the scan path adds about ½ a gate of delay (2%-ish).
Almost lost in the noise. Thanks.
Stefan
MitchAlsup1 wrote:
In the distant path, I had the select lines (the heavy loads that
cross the data path and select things for it to do) captured at
the other end of the data path with a skewable scan clock so we
could (essentially) see the timing of the select lines after
crossing the data path. This made it possible to use the scan
path as an oscilloscope.
Was that the AMD with the 6 phase clock you mentioned before?
I was wondering about how boundary scan would work with that.
I suppose you'd have 6 separate scan paths to capture each
phases logic states.
Actually, you're not far off. It's a serial shift chain which isEven state-of-the-art CPUs today commonly use scan-chains (via JTAG)Is there some blog somewhere that explains how scan-chains work (not
for debuggin.
how they're used, but how they're implemented inside the CPU)? >>>Intuitively they sound very costly to me, because of things like the
need to run extra wires all over the place. I'm obviously
missing something.
shifted
one-bit at a time to capture flop states. Each chain is a single wire;
a chip may have a few dozen individual shift chains.
https://www.design-reuse.com/articles/48331/scan-chains-pnr-outlook.html
Thanks. Wow. So it is really that bad, huh?
I also liked the note about speed limits and power consumption, how
shifting a state (in or out) causes (almost) all the flip-flops to
change state at each cycle, thus leading to very high power consumption.
What's the approximate cost of those scan chains. I.e. if we were to
take an existing working design and replace all the "flip-flop with scan-chain" with "plain flip-flops", how much smaller would the
resulting chip be, how much faster could it run, and how much less power could it consume?
I assume the cost in terms of power consumption is small because in
normal use, the scan-chain part stays completely stable so that barring leakage it should not consume any power, save for the indirect costs
like the need to move the other bits over greater distances when
the extra wires of the scan chains get in the way.
Stefan
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