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  • generating unneeded (silly) instructions

    From erwin.matthijssen@gmail.com@21:1/5 to All on Mon Mar 13 07:51:29 2017
    I am new to compilers so maybe what I am about to describe is normal behaviour. My current retargeting efforts are starting to generate working code. However, it has a lot of the instruction sequence below in there:

    #1 stw r1,-2(bp)
    #2 ldw r4, -2(bp)
    #3 addi r4,1,r4
    #4 stw r4,-2(bp)
    #5 ldw r1, -2(bp)

    We are storing something in memory from register-1 (R1). Then reloading that value in R4. Do something with it. Store it in memory. Then immediately reloading that again.

    It's obvious instructions #2 and #5 could be avoided with better register selection. Is this something i can tweak in my .md file somehow? Or is this just normal compiler behaviour?

    Thanks,
    Erwin

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  • From jacobnavia@21:1/5 to All on Mon Mar 13 16:52:52 2017
    Le 13/03/2017 à 15:51, erwin.matthijssen@gmail.com a écrit :
    I am new to compilers so maybe what I am about to describe is normal behaviour. My current retargeting efforts are starting to generate working code. However, it has a lot of the instruction sequence below in there:

    #1 stw r1,-2(bp)
    #2 ldw r4, -2(bp)
    #3 addi r4,1,r4
    #4 stw r4,-2(bp)
    #5 ldw r1, -2(bp)

    We are storing something in memory from register-1 (R1). Then reloading that value in R4. Do something with it. Store it in memory. Then immediately reloading that again.

    It's obvious instructions #2 and #5 could be avoided with better register selection. Is this something i can tweak in my .md file somehow? Or is this just normal compiler behaviour?

    Thanks,
    Erwin


    There are two steps

    1) Make it work
    2) Make it work better.

    Please do step (1) before attempting to do step (2)

    I have built for the x86 a peephole optimizer that will eliminate those unneeded instruction but that is step (2). Just make it work first.

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  • From erwin.matthijssen@gmail.com@21:1/5 to All on Mon Mar 13 10:14:46 2017
    I fully agree of course.

    I was just wondering if there was something obvious I was missing in the lcc machine description language.

    What I gather is that any optimisation for these types of occurrences will be separate from lcc.

    Thx,
    Erwin

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  • From jacobnavia@21:1/5 to All on Mon Mar 13 18:21:27 2017
    Le 13/03/2017 à 18:14, erwin.matthijssen@gmail.com a écrit :
    I fully agree of course.

    I was just wondering if there was something obvious I was missing in the lcc machine description language.

    What I gather is that any optimisation for these types of occurrences will be separate from lcc.

    Thx,
    Erwin

    You can do longer sequences to avoid intermediate results.

    For instance I have a rule like this in the x86 machine

    ADDP(ADDL(LSHL(reg,icon),acon),reg) "\tleaq\t%2(%3Q,%0,%1),%cQ\n"

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