The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.It's a pity that the indentation was screwed up by the new post tool :(
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron Plichota
On Wednesday, November 30, 2022 at 7:55:49 AM UTC-5, Myron Plichota wrote:[...]
e.g. apps/color_toy.py:
It's a pity that the indentation was screwed up by the new post tool :(
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron Plichota
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:CDP1802! I cut my teeth on that axe and began my love/hate relationship with Forth in COSMAC land.
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:I have built Lattice iCE40 HX1k and HX8k stack-machine SoCs for the iCEstick and EB85.
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ This has definite transplant potential. It uses the same XC7S25 FPGA.
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small. And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA. But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM available
I do not recommend that board.
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:A quick review of the FPGA datasheet shows problems:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small. And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
And regarding 0.1" pitch: I have used this solution in the past:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice. https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA. But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM available
I do not recommend that board.
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:serial port.
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA. But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
That would be called "semi-dual port" mode.
2) there is a maximum of 26Kx18-bits block RAM available
Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.
For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:serial port.
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA. But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a
--Popping the stack:
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
On Monday, 5 December 2022 at 08:38:14 UTC, Myron Plichota wrote:I jumped to the conclusion that this conversation topic wandered into candidate FPGAs for a BugsBoard transplant. My comments are motivated by the desire to spare adopters time and money, if they wish to perform said transplant (which is not a trivial
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA. But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
I think we are looking at this the wrong way around.And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM available
I do not recommend that board.
I just picked one of the large variety there that seemed to fit nicely regarding prototyping and breadboard and had USB.
You are the specialist who knows what you want to your applications.
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:a serial port.
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and
--
Rick C.
- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:and a serial port.
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years. If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past: male headers soldered into the boardA quick review of the FPGA datasheet shows problems:
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming,
Meanwhile, hot off the press:--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
+-- Get 1,000 miles of free SuperchargingPlease take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
+-- Tesla referral code - https://ts.la/richard11209
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:and a serial port.
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past: male headers soldered into the boardA quick review of the FPGA datasheet shows problems:
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming,
Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209
On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:and a serial port.
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years. If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past: male headers soldered into the boardA quick review of the FPGA datasheet shows problems:
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming,
--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
+-- Get 1,000 miles of free SuperchargingPlease take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
+-- Tesla referral code - https://ts.la/richard11209
On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:programming, and a serial port.
On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past: male headers soldered into the boardA quick review of the FPGA datasheet shows problems:
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG
How 'bout you take a look at it and decide for yourself?--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?+-- Get 1,000 miles of free SuperchargingPlease take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
+-- Tesla referral code - https://ts.la/richard11209
--
Rick C.
-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209
On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:programming, and a serial port.
On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG
--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?+-- Get 1,000 miles of free SuperchargingPlease take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
+-- Tesla referral code - https://ts.la/richard11209
--
Rick C.
-- Get 1,000 miles of free SuperchargingHow 'bout you take a look at it and decide for yourself?
-- Tesla referral code - https://ts.la/richard11209
On Thursday, December 8, 2022 at 3:02:51 AM UTC-5, gnuarm.del...@gmail.com wrote:programming, and a serial port.
On Thursday, December 8, 2022 at 2:55:02 AM UTC-4, Myron Plichota wrote:
On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG
--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?+-- Get 1,000 miles of free SuperchargingPlease take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
+-- Tesla referral code - https://ts.la/richard11209
--
Rick C.
Sure, as soon as I find time to look at a random piece of code someone has not said anything about.-- Get 1,000 miles of free SuperchargingHow 'bout you take a look at it and decide for yourself?
-- Tesla referral code - https://ts.la/richard11209
Thanks...
--
Rick C.
-+ Get 1,000 miles of free Superchargingram1c.v is in the Verilog directory within Bugs18bis.zip. Perhaps you will be the first one to say something about it.
-+ Tesla referral code - https://ts.la/richard11209
On Thursday, December 8, 2022 at 2:55:02 AM UTC-4, Myron Plichota wrote:programming, and a serial port.
On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG
ram1c.v is in the Verilog directory within Bugs18bis.zip. Perhaps you will be the first one to say something about it.--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?+-- Get 1,000 miles of free SuperchargingPlease take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
+-- Tesla referral code - https://ts.la/richard11209
--
Rick C.
Sure, as soon as I find time to look at a random piece of code someone has not said anything about.-- Get 1,000 miles of free SuperchargingHow 'bout you take a look at it and decide for yourself?
-- Tesla referral code - https://ts.la/richard11209
Thanks...
--
Rick C.
-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
On Thursday, December 8, 2022 at 4:16:38 AM UTC-4, Myron Plichota wrote:programming, and a serial port.
On Thursday, December 8, 2022 at 3:02:51 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Thursday, December 8, 2022 at 2:55:02 AM UTC-4, Myron Plichota wrote:
On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG
Bugs18bis.zip is at https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=share_link--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?+-- Get 1,000 miles of free SuperchargingPlease take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
+-- Tesla referral code - https://ts.la/richard11209
--
Rick C.
Sure, as soon as I find time to look at a random piece of code someone has not said anything about.-- Get 1,000 miles of free SuperchargingHow 'bout you take a look at it and decide for yourself?
-- Tesla referral code - https://ts.la/richard11209
Thanks...
--
Rick C.
So where do I find this zip file?-+ Get 1,000 miles of free Superchargingram1c.v is in the Verilog directory within Bugs18bis.zip. Perhaps you will be the first one to say something about it.
-+ Tesla referral code - https://ts.la/richard11209
--
Rick C.
+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
In article <b8411641-e13d-46b7...@googlegroups.com>,Relax, it's nothing that concerns you.
How 'bout you take a look at it and decide for yourself?How to snip a lines that are not relevant so that we can understand
what you're talking about?
Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst
How 'bout you take a look at it and decide for yourself?
On Thursday, December 8, 2022 at 3:58:43 AM UTC-5, gnuarm.del...@gmail.com wrote:programming, and a serial port.
On Thursday, December 8, 2022 at 4:16:38 AM UTC-4, Myron Plichota wrote:
On Thursday, December 8, 2022 at 3:02:51 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Thursday, December 8, 2022 at 2:55:02 AM UTC-4, Myron Plichota wrote:
On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
e.g. apps/color_toy.py:
include('FPGAburn/appload.py') # must be on the first line
# play with LD0 color
ja(fwd('init'))
lbl('app_msg'); ascii('\r\npress BTN0 to reset')
# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])
# commands
lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()
lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()
lbl('ig') # char -> # increment green drop(); lld(green); inc(); lst(green); ret()
lbl('dg') # char -> # decrement green drop(); lld(green); dec(); lst(green); ret()
lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()
lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()
lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()
lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()
lbl('app_end') # must be on the last line
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron PlichotaThe number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.
I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.Nandland board $65, https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the momentFPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
https://shop.pimoroni.com/search?q=fpga%20board But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.There are so many versions on the website, this one might fit better for you
I'd be delighted to hear about succesful mutations on other FPGA-based boards.
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
That would be called "semi-dual port" mode.And regarding 0.1" pitch: I have used this solution in the past:A quick review of the FPGA datasheet shows problems:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM availableEvery part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
I do not recommend that board.For what?
If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG
--
Rick C.
Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?- Get 1,000 miles of free SuperchargingPopping the stack:
- Tesla referral code - https://ts.la/richard11209
1) Q: do not recommend for what? A: a BugsBoard transplant 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
--
Rick C.
I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?+-- Get 1,000 miles of free SuperchargingPlease take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
+-- Tesla referral code - https://ts.la/richard11209
--
Rick C.
Sure, as soon as I find time to look at a random piece of code someone has not said anything about.-- Get 1,000 miles of free SuperchargingHow 'bout you take a look at it and decide for yourself?
-- Tesla referral code - https://ts.la/richard11209
Thanks...
--
Rick C.
So where do I find this zip file?-+ Get 1,000 miles of free Superchargingram1c.v is in the Verilog directory within Bugs18bis.zip. Perhaps you will be the first one to say something about it.
-+ Tesla referral code - https://ts.la/richard11209
--
Rick C.
+- Get 1,000 miles of free SuperchargingBugs18bis.zip is at https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=share_link
+- Tesla referral code - https://ts.la/richard11209
BTW this link is also in the downloads section of BugsBoard_Primer.pdf at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
I tried to convey this info in my kickoff post, but I'm a geek, not a salesman.
On Thursday, December 8, 2022 at 5:36:59 AM UTC-4, Myron Plichota wrote:
Bugs18bis.zip is at https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=share_linkI looked at the file. You wish to use opposite edges of the clock for read and write.
BTW this link is also in the downloads section of BugsBoard_Primer.pdf at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
I tried to convey this info in my kickoff post, but I'm a geek, not a salesman.
Before I make any comments, I want to ask, why was it necessary for me to read the file in order for you to ask a question?
On Thursday, December 8, 2022 at 10:13:04 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Thursday, December 8, 2022 at 5:36:59 AM UTC-4, Myron Plichota wrote:
Bugs18bis.zip is at https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=share_linkI looked at the file. You wish to use opposite edges of the clock for read and write.
BTW this link is also in the downloads section of BugsBoard_Primer.pdf at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
I tried to convey this info in my kickoff post, but I'm a geek, not a salesman.
Before I make any comments, I want to ask, why was it necessary for me to read the file in order for you to ask a question?For the same reason that I follow links posted here before I add my 2 cents. Otherwise, I wouldn't know what questions to ask, or have a factual basis for my opinion. Was it such an ordeal viewing 25 lines of Verilog?
On Friday, December 9, 2022 at 6:14:50 AM UTC-4, Myron Plichota wrote:clock on opposite edges of the clock, you travel down a rabbit hole of obstruction.
On Thursday, December 8, 2022 at 10:13:04 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Thursday, December 8, 2022 at 5:36:59 AM UTC-4, Myron Plichota wrote:
Bugs18bis.zip is at https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=share_linkI looked at the file. You wish to use opposite edges of the clock for read and write.
BTW this link is also in the downloads section of BugsBoard_Primer.pdf at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
I tried to convey this info in my kickoff post, but I'm a geek, not a salesman.
It was pointless, just as this entire discussion. You seem to enjoy distracting from the conversation, rather than promoting a conversation. You posted that you didn't like a board, without explaining why. When asked, rather than saying, you need toBefore I make any comments, I want to ask, why was it necessary for me to read the file in order for you to ask a question?For the same reason that I follow links posted here before I add my 2 cents. Otherwise, I wouldn't know what questions to ask, or have a factual basis for my opinion. Was it such an ordeal viewing 25 lines of Verilog?
In the end, I found that your complaint is baseless. You don't seem to understand block RAMs, or at least don't understand the Gowin BRAMs. Did you try synthesizing this file? Again, no information from you on this.
You didn't post your 2 cents. You posted noise.
In response to your file, what you would use is Semi-Dual Port Mode.
Now, learn how to have a discussion rather than being a bit of a jerk. Oh, and you are welcome for the advice on how to use the Gowin BRAM.
--
Rick C.
--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209
On Friday, 9 December 2022 at 11:50:24 UTC, gnuarm.del...@gmail.com wrote:clock on opposite edges of the clock, you travel down a rabbit hole of obstruction.
On Friday, December 9, 2022 at 6:14:50 AM UTC-4, Myron Plichota wrote:
On Thursday, December 8, 2022 at 10:13:04 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Thursday, December 8, 2022 at 5:36:59 AM UTC-4, Myron Plichota wrote:
Bugs18bis.zip is at https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=share_linkI looked at the file. You wish to use opposite edges of the clock for read and write.
BTW this link is also in the downloads section of BugsBoard_Primer.pdf at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
I tried to convey this info in my kickoff post, but I'm a geek, not a salesman.
It was pointless, just as this entire discussion. You seem to enjoy distracting from the conversation, rather than promoting a conversation. You posted that you didn't like a board, without explaining why. When asked, rather than saying, you need toBefore I make any comments, I want to ask, why was it necessary for me to read the file in order for you to ask a question?For the same reason that I follow links posted here before I add my 2 cents. Otherwise, I wouldn't know what questions to ask, or have a factual basis for my opinion. Was it such an ordeal viewing 25 lines of Verilog?
In the end, I found that your complaint is baseless. You don't seem to understand block RAMs, or at least don't understand the Gowin BRAMs. Did you try synthesizing this file? Again, no information from you on this.
You didn't post your 2 cents. You posted noise.
In response to your file, what you would use is Semi-Dual Port Mode.
Now, learn how to have a discussion rather than being a bit of a jerk. Oh, and you are welcome for the advice on how to use the Gowin BRAM.
--
Rick C.
--- Get 1,000 miles of free SuperchargingThere is you again who puts his nasty-guy hat on.
--- Tesla referral code - https://ts.la/richard11209
Your reading capabilities seem to have unfortunately dedetiorated drastically.
Myron explained it all.
Everything Myron posted made sense.
And the link was in his first post.
BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.
Cheers - Myron Plichota
GET YOUR READING GLASSES.
The reality is Myron doesn't understand the Gowin BSRAM. That was the point. Rather than ask me a simple question about how to use the Gowin BRAM, he drags it out like a drama queen. Then when I finally find out that the issue was about Myron notunderstanding the parts and giving Gowin a black eye with his false comments, I explained the point to him. Was I rude, not really. Was I sweet as pie, no, not at all. I don't have patience for drama queens. You are at the top of that list. You mainly
The Gowin BSRAM will support a read port and a write port with separate data and clocks. For an unknown reason, Myron thought that would be supported in single port mode. The very wording of "single" port mode says you can't have two of anything. Dualport mode will support his RAM file, except there is one configuration of address and data bus size that is not available, 32/36 bit data. The semi-dual port mode with two separate interfaces for read and write, are exactly what Myron is describing in
Now you both know and have no reason to complain. But I'm sure you will find plenty to complain about. That's what you do, oh so well. But in any event, you are welcome for the lesson in Gowin BSRAMs.[snip]
On Friday, December 9, 2022 at 4:59:06 PM UTC-5, gnuarm.del...@gmail.com wrote:understanding the parts and giving Gowin a black eye with his false comments, I explained the point to him. Was I rude, not really. Was I sweet as pie, no, not at all. I don't have patience for drama queens. You are at the top of that list. You mainly
[snip]
Thanks for your kind defence, Juergen.
[snip]
The reality is Myron doesn't understand the Gowin BSRAM. That was the point. Rather than ask me a simple question about how to use the Gowin BRAM, he drags it out like a drama queen. Then when I finally find out that the issue was about Myron not
Dual port mode will support his RAM file, except there is one configuration of address and data bus size that is not available, 32/36 bit data. The semi-dual port mode with two separate interfaces for read and write, are exactly what Myron is describingThe Gowin BSRAM will support a read port and a write port with separate data and clocks. For an unknown reason, Myron thought that would be supported in single port mode. The very wording of "single" port mode says you can't have two of anything.
still do not recommend this FPGA for a BugsBoard transplant. Semi dual port mode is not a solution to my design problem.Now you both know and have no reason to complain. But I'm sure you will find plenty to complain about. That's what you do, oh so well. But in any event, you are welcome for the lesson in Gowin BSRAMs.[snip]
Well at least I pointed and clicked and registered a new Gowin account (had to give the bastards my email@) and downloaded the datasheet and searched within for BRAM info and spent a few minutes assessing the graphics and text. After repeated views, I
OTOH, the datasheets for Lattice iCE40 and Xilinx Series 7 FPGAs show single-port BRAM modes with selectable clock polarity for the read and write clocks. Bingo, the solution to my design problem, i.e. make synchronous BRAM yield any random read with 1-clock latency (0 wait states, no CPU stalls). ram1c.v *infers* correct single-port BRAM aggregates using the Lattice iCEcube2 and Xilinx Vivado ML 2021.1 toolchains, as proven by multiple projects.
But don't let me hold you back, Rick. I hope that someday you will publish solutions you are humbly proud of.
"Jimbo is not James Bond, except when he is." - an ancient koan
On Friday, December 9, 2022 at 4:59:06 PM UTC-5, gnuarm.del...@gmail.com wrote:understanding the parts and giving Gowin a black eye with his false comments, I explained the point to him. Was I rude, not really. Was I sweet as pie, no, not at all. I don't have patience for drama queens. You are at the top of that list. You mainly
[snip]
Thanks for your kind defence, Juergen.
[snip]
The reality is Myron doesn't understand the Gowin BSRAM. That was the point. Rather than ask me a simple question about how to use the Gowin BRAM, he drags it out like a drama queen. Then when I finally find out that the issue was about Myron not
Dual port mode will support his RAM file, except there is one configuration of address and data bus size that is not available, 32/36 bit data. The semi-dual port mode with two separate interfaces for read and write, are exactly what Myron is describingThe Gowin BSRAM will support a read port and a write port with separate data and clocks. For an unknown reason, Myron thought that would be supported in single port mode. The very wording of "single" port mode says you can't have two of anything.
still do not recommend this FPGA for a BugsBoard transplant. Semi dual port mode is not a solution to my design problem.Now you both know and have no reason to complain. But I'm sure you will find plenty to complain about. That's what you do, oh so well. But in any event, you are welcome for the lesson in Gowin BSRAMs.[snip]
Well at least I pointed and clicked and registered a new Gowin account (had to give the bastards my email@) and downloaded the datasheet and searched within for BRAM info and spent a few minutes assessing the graphics and text. After repeated views, I
OTOH, the datasheets for Lattice iCE40 and Xilinx Series 7 FPGAs show single-port BRAM modes with selectable clock polarity for the read and write clocks. Bingo, the solution to my design problem, i.e. make synchronous BRAM yield any random read with 1-clock latency (0 wait states, no CPU stalls). ram1c.v *infers* correct single-port BRAM aggregates using the Lattice iCEcube2 and Xilinx Vivado ML 2021.1 toolchains, as proven by multiple projects.
But don't let me hold you back, Rick. I hope that someday you will publish solutions you are humbly proud of.
Poo itto baby can't undertand Bugs18bis.zip.
On Saturday, December 10, 2022 at 9:50:36 AM UTC-4, Myron Plichota wrote:
Poo itto baby can't undertand Bugs18bis.zip.So not only can you not explain your problem, just thinking about it reduces you to baby talk?
Dude, you are a trip!
On Saturday, December 10, 2022 at 9:57:46 AM UTC-5, gnuarm.del...@gmail.com wrote:
On Saturday, December 10, 2022 at 9:50:36 AM UTC-4, Myron Plichota wrote:
Poo itto baby can't undertand Bugs18bis.zip.So not only can you not explain your problem, just thinking about it reduces you to baby talk?
Dude, you are a trip!I'm on a very good trip that defies explaining color to a blind man.
Instead of all the crap, why not just answer the question? What is it about the Gowin BSRAM that makes you say, "Semi dual port mode is not a solution to my design problem."
On Saturday, December 10, 2022 at 1:56:41 PM UTC-5, gnuarm.del...@gmail.com wrote:
Instead of all the crap, why not just answer the question? What is it about the Gowin BSRAM that makes you say, "Semi dual port mode is not a solution to my design problem."1) You don't appear to have an interest in performing a BugsBoard transplant. 2) Even if you do, you deserve to fail.
I wish that clf culture relaxed a wee bit and became famous for promoting the merits of fundamental Forth programming precepts.
On Monday, 12 December 2022 at 01:12:21 UTC, Myron Plichota wrote:
On Saturday, December 10, 2022 at 1:56:41 PM UTC-5, gnuarm.del...@gmail.com wrote:What an ugly character this guy is.
Instead of all the crap, why not just answer the question? What is it about the Gowin BSRAM that makes you say, "Semi dual port mode is not a solution to my design problem."1) You don't appear to have an interest in performing a BugsBoard transplant.
2) Even if you do, you deserve to fail.
But the Forth community here has to live him/it until he dies,
or he gets more direct feedback from others here and leaves to bother other groups that cannot throw him/it out.
A little statistic regardig this post:
327 people looked at it
7 people reacted and posted
So, I think this is a great post of yours, especially when Verilog can be expressed in Forth;
but for now it might be actually the wrong group to post it in as the reaction shows.
On Sunday, August 20, 2023 at 6:35:21 PM UTC-7, Myron Plichota wrote:
I wish that clf culture relaxed a wee bit and became famous for promoting the merits of fundamental Forth programming precepts.I remember that I told you about Testra's MiniForth built on the Lattice isp1048 PLD in 1995 and how it held the data-stack in external memory.
My processor design also holds the data-stack in memory (internal now).
You said that myself and everybody at Testra should take a Programming-101 class to learn basic programming concepts. You seem to think that the only viable solution for a Forth processor is to hold the entire data-stack in cell flip-flops so that Forth words such as DUP SWAP OVER + etc. can be single clock-cycle. The data-stack would be fairly small, like 8 elements. There are actually serious problems with this technique. For one thing,
you can't have ISRs because you have no way to save/restore the Forth context.
I think that you could really relax a wee bit too --- dial down the arrogance!
The MiniForth was used in a a motion-control board that was less-expensive and higher-performing than the competition's motion-control board that used an MC68000 programmed in C. Has the Bugs18 processor ever competed successfully with C? Has it ever been used in a real-world application?
This is the year 2023 --- the MiniForth came out in 1995 --- nobody in the Forth community has come up with anything comparable after three decades.
Your Bugs18 has a 6-bit opcode, so there are 64 instructions.
That is not very many! There is no future in a processor with only 64 instructions --- this is a toy --- it will never be used for real-world applications.
Why can't stack processors with small instructions be useful in real world applications?
On Sunday, August 20, 2023 at 6:35:21 PM UTC-7, Myron Plichota wrote:
I wish that clf culture relaxed a wee bit and became famous for promoting the merits of fundamental Forth programming precepts.I remember that I told you about Testra's MiniForth built on the Lattice isp1048 PLD in 1995 and how it held the data-stack in external memory.
My processor design also holds the data-stack in memory (internal now).
You said that myself and everybody at Testra should take a Programming-101 class to learn basic programming concepts. You seem to think that the only viable solution for a Forth processor is to hold the entire data-stack in cell flip-flops so that Forth words such as DUP SWAP OVER + etc. can be single clock-cycle.
The data-stack would be fairly small, like 8 elements.
There are actually serious problems with this technique. For one thing,
you can't have ISRs because you have no way to save/restore the Forth context.
I think that you could really relax a wee bit too --- dial down the arrogance!
The MiniForth was used in a a motion-control board that was less-expensive and higher-performing than the competition's motion-control board that used an MC68000 programmed in C. Has the Bugs18 processor ever competed successfully with C? Has it ever been used in a real-world application?
This is the year 2023 --- the MiniForth came out in 1995 --- nobody in the Forth community has come up with anything comparable after three decades.
Your Bugs18 has a 6-bit opcode, so there are 64 instructions.
That is not very many! There is no future in a processor with only 64 instructions --- this is a toy --- it will never be used for real-world applications.
Is your processor single clock per instruction? What is the max clock rate?Yes. A modest 48 MHz.
Why can't stack processors with small instructions be useful in real world applications?I have demonstrated that they are up to audio bandwidth.
Is your processor single clock per instruction? What is the max clock rate?Yes. A modest 48 MHz.
On Monday, August 21, 2023 at 1:48:44 AM UTC-4, Myron Plichota wrote:looping capability (hard to think it wouldn't). It was designed to capture an ADC sample and run through the code once, lather, rinse, repeat.
That's a promising capability. I recall a couple of families of audio processors for hearing aids, that were just designed to handle the signal processing, such as filters. The architecture was a linear set of instructions, which might have had someIs your processor single clock per instruction? What is the max clock rate?Yes. A modest 48 MHz.
I never obtained details of the instructions or architecture, because the makers were mainly interested in large buyer. My production quantities range around 1,000 to 3,000 units per year these days, not enough to interest these guys.
I always appealed to me. They were pretty low power and clearly optimized for audio work. One supplier was ADI. I took a quick look, and the units I had seen seem to be out of date now. Here's one that's pretty powerful.
https://www.onsemi.com/download/data-sheet/pdf/e7111-d.pdf
There's lots of stuff on the market.
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