On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
jrh
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:Looking forward to it.
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
jrh
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it.
http://www.forth.org/svfig/
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:Looking forward to it.
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
jrh
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it.
http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:Looking forward to it.
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
jrh
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it.
http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth. See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote: >> On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
jpit...@gmail.com wrote:On Thursday, November 25, 2021 at 2:39:20 AM UTC-7,
The Logic Compiler is working and the modules for the processor are doneOn Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
and tested. After the mem interface module is complete we'll be ready to
put the design into the fpga. We're using a X02-7000 but the design will
work in any equivalent part.
jrh
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:part.
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it.
http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:equivalent part.
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description,Maybe we are hitting a language barrier.
but it sounds like it is for CPLDs, rather than FPGAs.
--
Rick C.
-+- Get 1,000 miles of free SuperchargingThe linfo at Testra clearly states:
-+- Tesla referral code - https://ts.la/richard11209
Using Forth as a VHDL ( Virtual Hardware Definition Language )
John R. Hart, Testra Corporation
They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
You have all of the advantages of Forth,
and no need for the overhead of FPGA tools as I understand.
I am surprised this has not been of interest for the last many years,
as the info on the Testra website was always there.
But now we hopefully get the opportunity to see a full example.
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:part.
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
Maybe we are hitting a language barrier.jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description,
but it sounds like it is for CPLDs, rather than FPGAs.
--
Rick C.
-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209
On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:equivalent part.
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description,Maybe we are hitting a language barrier.
but it sounds like it is for CPLDs, rather than FPGAs.
--
Rick C.
-+- Get 1,000 miles of free SuperchargingThe linfo at Testra clearly states:
-+- Tesla referral code - https://ts.la/richard11209
Using Forth as a VHDL ( Virtual Hardware Definition Language )
John R. Hart, Testra Corporation
They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
You have all of the advantages of Forth,
and no need for the overhead of FPGA tools as I understand.
I am surprised this has not been of interest for the last many years,
as the info on the Testra website was always there.
But now we hopefully get the opportunity to see a full example.
On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:equivalent part.
On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description,Maybe we are hitting a language barrier.
but it sounds like it is for CPLDs, rather than FPGAs.
--
Rick C.
-+- Get 1,000 miles of free SuperchargingThe linfo at Testra clearly states:
-+- Tesla referral code - https://ts.la/richard11209
Using Forth as a VHDL ( Virtual Hardware Definition Language )Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
John R. Hart, Testra Corporation
They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
You have all of the advantages of Forth,It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000
and no need for the overhead of FPGA tools as I understand.
I am surprised this has not been of interest for the last many years,Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
as the info on the Testra website was always there.
But now we hopefully get the opportunity to see a full example."Full example"???
It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
1. Write the design in VHDL or Verilog
2. Write a test bench for the simulation stimulus and error checking.
3. Simulate the design using conventional simulators.
4. Synthesize the design for the target chip.
5. Test on the target board.
Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
--
Rick C.
-++ Get 1,000 miles of free SuperchargingI am sorry, but your post does not make sense to me.
-++ Tesla referral code - https://ts.la/richard11209
Testra use this setup for many years in their products
and it must make sense there,
otherwise they would just use the standard Lattice tools.
If it is not relevant to you - fine - I never asked you.
Just like asking an experienced C programmer - why not Forth ...
On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:equivalent part.
On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description,Maybe we are hitting a language barrier.
but it sounds like it is for CPLDs, rather than FPGAs.
--
Rick C.
-+- Get 1,000 miles of free SuperchargingThe linfo at Testra clearly states:
-+- Tesla referral code - https://ts.la/richard11209
Using Forth as a VHDL ( Virtual Hardware Definition Language )Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
John R. Hart, Testra Corporation
They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
You have all of the advantages of Forth,It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000
and no need for the overhead of FPGA tools as I understand.
I am surprised this has not been of interest for the last many years,Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
as the info on the Testra website was always there.
But now we hopefully get the opportunity to see a full example."Full example"???
It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
1. Write the design in VHDL or Verilog
2. Write a test bench for the simulation stimulus and error checking.
3. Simulate the design using conventional simulators.
4. Synthesize the design for the target chip.
5. Test on the target board.
Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
--
Rick C.
-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209
On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:equivalent part.
On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description,Maybe we are hitting a language barrier.
but it sounds like it is for CPLDs, rather than FPGAs.
--
Rick C.
-+- Get 1,000 miles of free SuperchargingThe linfo at Testra clearly states:
-+- Tesla referral code - https://ts.la/richard11209
Using Forth as a VHDL ( Virtual Hardware Definition Language )Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
John R. Hart, Testra Corporation
They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
You have all of the advantages of Forth,It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-
and no need for the overhead of FPGA tools as I understand.
additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, becauseI am surprised this has not been of interest for the last many years, as the info on the Testra website was always there.Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
But now we hopefully get the opportunity to see a full example."Full example"???
It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
1. Write the design in VHDL or Verilog
2. Write a test bench for the simulation stimulus and error checking.
3. Simulate the design using conventional simulators.
4. Synthesize the design for the target chip.
5. Test on the target board.
Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
--
Rick C.
-++ Get 1,000 miles of free SuperchargingI am sorry, but your post does not make sense to me.
-++ Tesla referral code - https://ts.la/richard11209
Testra use this setup for many years in their products
and it must make sense there,
otherwise they would just use the standard Lattice tools.
If it is not relevant to you - fine - I never asked you.LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!
Just like asking an experienced C programmer - why not Forth ...
The millions of users of VHDL and Verilog must have it wrong.
One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design
In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
Thank you for the information.
--
Rick C.
+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209
On Tuesday, October 11, 2022 at 9:54:49 AM UTC-4, jpit...@gmail.com wrote:equivalent part.
On Monday, 10 October 2022 at 16:52:33 UTC+1, gnuarm.del...@gmail.com wrote:
On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:
On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition. 4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description, but it sounds like it is for CPLDs, rather than FPGAs.Maybe we are hitting a language barrier.
--
Rick C.
-+- Get 1,000 miles of free SuperchargingThe linfo at Testra clearly states:
-+- Tesla referral code - https://ts.la/richard11209
Using Forth as a VHDL ( Virtual Hardware Definition Language ) John R. Hart, Testra CorporationAh, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
You have all of the advantages of Forth,It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-
and no need for the overhead of FPGA tools as I understand.
additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, becauseI am surprised this has not been of interest for the last many years,Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
as the info on the Testra website was always there.
But now we hopefully get the opportunity to see a full example."Full example"???
It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
1. Write the design in VHDL or Verilog
2. Write a test bench for the simulation stimulus and error checking.
3. Simulate the design using conventional simulators.
4. Synthesize the design for the target chip.
5. Test on the target board.
Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
--
Rick C.
-++ Get 1,000 miles of free SuperchargingI am sorry, but your post does not make sense to me.
-++ Tesla referral code - https://ts.la/richard11209
Testra use this setup for many years in their products
and it must make sense there,
otherwise they would just use the standard Lattice tools.
If it is not relevant to you - fine - I never asked you.LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!
Just like asking an experienced C programmer - why not Forth ...
The millions of users of VHDL and Verilog must have it wrong.
One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design
is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. In reality,In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
Thank you for the information.
--
Rick C.
"Others"??? You mean "other", I think.+-- Get 1,000 miles of free SuperchargingIt seems there are others working in the corner that are interested in this subject,
+-- Tesla referral code - https://ts.la/richard11209
see about 46.00 onwards, e.g. gelforth https://www.youtube.com/watch?v=ASgBoKisWac
Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design, which
I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If thatwere true, why has nothing happened with it in the last six years?
People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The existingtools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.
--
Rick C.
+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209
On Monday, 10 October 2022 at 16:52:33 UTC+1, gnuarm.del...@gmail.com wrote:equivalent part.
On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:
On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition. 4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description,Maybe we are hitting a language barrier.
but it sounds like it is for CPLDs, rather than FPGAs.
--
Rick C.
-+- Get 1,000 miles of free SuperchargingThe linfo at Testra clearly states:
-+- Tesla referral code - https://ts.la/richard11209
Using Forth as a VHDL ( Virtual Hardware Definition Language )Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
John R. Hart, Testra Corporation
They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
You have all of the advantages of Forth,It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-
and no need for the overhead of FPGA tools as I understand.
additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, becauseI am surprised this has not been of interest for the last many years,Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
as the info on the Testra website was always there.
But now we hopefully get the opportunity to see a full example."Full example"???
It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
1. Write the design in VHDL or Verilog
2. Write a test bench for the simulation stimulus and error checking. 3. Simulate the design using conventional simulators.
4. Synthesize the design for the target chip.
5. Test on the target board.
Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
--
Rick C.
-++ Get 1,000 miles of free SuperchargingI am sorry, but your post does not make sense to me.
-++ Tesla referral code - https://ts.la/richard11209
Testra use this setup for many years in their products
and it must make sense there,
otherwise they would just use the standard Lattice tools.
If it is not relevant to you - fine - I never asked you.LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!
Just like asking an experienced C programmer - why not Forth ...
The millions of users of VHDL and Verilog must have it wrong.
One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design
In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
Thank you for the information.
--
Rick C.
+-- Get 1,000 miles of free SuperchargingIt seems there are others working in the corner that are interested in this subject,
+-- Tesla referral code - https://ts.la/richard11209
see about 46.00 onwards, e.g. gelforth https://www.youtube.com/watch?v=ASgBoKisWac
Well, there seems to be only "ONE PERSON" who does not like this.It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will...
Well, there seems to be only "ONE PERSON" who does not like this.It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will...
Jurgen,
As I read Rick's response I had to smile.
Not knowing it, he summed up the reasons why authoritarian systems don't work.
The reason Forth is useful is its extensibility;
can be turned into any tool one wants, including a verilog code generator. Then, even if the result isn't perfect, one can edit the output to one's heart's content, which of course is what I do.
A more difficult aspect of logic design is verifying it works.
To do so one needs a reference to compare with. Forth, being extensible, is the ideal tool, especially when designing a Forth processor.
To create the new processor's software model took about a week,
and it was easy to modify as the design progressed.
The SW model provides the data needed by the hardware simulator to verify the verilog code is working.
Rapid specific feedback is the key to perfecting complex logic designs.
jrh
even if the result isn't perfect, one can edit the output to one's heart's content, which of course is what I do.Jurgen,Well, there seems to be only "ONE PERSON" who does not like this.It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will...
As I read Rick's response I had to smile. Not knowing it, he summed up the reasons why authoritarian systems don't work. The reason Forth is useful is its extensibility; can be turned into any tool one wants, including a verilog code generator. Then,
A more difficult aspect of logic design is verifying it works. To do so one needs a reference to compare with. Forth, being extensible, is the ideal tool, especially when designing a Forth processor.key to perfecting complex logic designs.
To create the new processor's software model took about a week, and it was easy to modify as the design progressed. The SW model provides the data needed by the hardware simulator to verify the verilog code is working. Rapid specific feedback is the
jrh
On Tuesday, 11 October 2022 at 15:46:54 UTC+1, gnuarm.del...@gmail.com wrote:any equivalent part.
On Tuesday, October 11, 2022 at 9:54:49 AM UTC-4, jpit...@gmail.com wrote:
On Monday, 10 October 2022 at 16:52:33 UTC+1, gnuarm.del...@gmail.com wrote:
On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:
On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
\ Op Code File for MFX. Generated by MAKE-OPS v13
X02-7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.jrhLooking forward to it.
Posting and distributing it in different places including facembbok should be easy.
An idea crossed my mind:Just for people who might not know the context:
Why not do a presentation during a FIG Zoom?
And this would help with where to post it. http://www.forth.org/svfig/
Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
See the link to Testra where it has been done already. http://testra.com/Forth/VHDL.htm
And hopefully there is more soon from Testra posted here..Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
--
Rick C.
--+ Get 1,000 miles of free SuperchargingYou are proving again that you attention span is zero - or is it your reading capability?
--+ Tesla referral code - https://ts.la/richard11209
Designing logic with the Forth VHDL
1. Write a software simulation of the design."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.
I can't tell what you are talking about from this description, but it sounds like it is for CPLDs, rather than FPGAs.Maybe we are hitting a language barrier.
--
Rick C.
-+- Get 1,000 miles of free SuperchargingThe linfo at Testra clearly states:
-+- Tesla referral code - https://ts.la/richard11209
Using Forth as a VHDL ( Virtual Hardware Definition Language ) John R. Hart, Testra CorporationAh, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere it could probably be ported to
other FPGA families.
You have all of the advantages of Forth,It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the
and no need for the overhead of FPGA tools as I understand.
design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages,I am surprised this has not been of interest for the last many years,Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
as the info on the Testra website was always there.
But now we hopefully get the opportunity to see a full example."Full example"???
It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
1. Write the design in VHDL or Verilog
2. Write a test bench for the simulation stimulus and error checking.
3. Simulate the design using conventional simulators.
4. Synthesize the design for the target chip.
5. Test on the target board.
Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
--
Rick C.
-++ Get 1,000 miles of free SuperchargingI am sorry, but your post does not make sense to me.
-++ Tesla referral code - https://ts.la/richard11209
Testra use this setup for many years in their products
and it must make sense there,
otherwise they would just use the standard Lattice tools.
If it is not relevant to you - fine - I never asked you.LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!
Just like asking an experienced C programmer - why not Forth ...
The millions of users of VHDL and Verilog must have it wrong.
One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my
which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. InIn this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
Thank you for the information.
--
Rick C.
"Others"??? You mean "other", I think.+-- Get 1,000 miles of free SuperchargingIt seems there are others working in the corner that are interested in this subject,
+-- Tesla referral code - https://ts.la/richard11209
see about 46.00 onwards, e.g. gelforth https://www.youtube.com/watch?v=ASgBoKisWac
Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design,
were true, why has nothing happened with it in the last six years?I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If that
existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The
I respect Rick C's opinions on the art of FPGA design. IMHO his comments are incisive and reality-oriented. I'm pretty sure he has experience in the matter.--
Rick C.
+-+ Get 1,000 miles of free SuperchargingWell, there seems to be only "ONE PERSON" who does not like this.
+-+ Tesla referral code - https://ts.la/richard11209
As there are 2 or three people who see it as interesting,
your importance with your comments is going down to a third.
AND:
The number of your posts does NOT increase the importance or value.
And there might be a Forth Person anyway ...
any equivalent part.The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in
Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done
many, many times, some published, many not published. It would seem to be a trivial exercise.
Rick C.
<clip>Designing logic with the Forth VHDL
1. Write a software simulation of the design. (Forth with local varables and a MAP extension)
2. Test the design. (test program, simple compiler and simulator written in Forth)
3. Convert the simulation into a hardware definition. (ED-MGEN, ED-CTRL, ED-DFRW, ED-DCDM, ED-DSEL)
4. Link instructions to modules. (EDIT-TRAN)
5. Compile the hardware definition into logic equations. (GEN-MAP, CTRL-MAP & DFRW-MAP programs}
6. Verify the logic equations work correctly. (EDIT-DISP, SIM-R32)
7. Assign the I/O pins. (ED-PINS, able to parse the csv pin file and combine it with the schematic foot print)
8. Fit the logic equations into the device. (Diamond from Lattice Semi does this, and there are universal ones)
9. Convert the routed design into a fusemap. (Diamond)
10. Compile the OS using the OP code definition file. (MAKE-OPS)
Our first CNC product had three 8032 processors. One for motion, One to process files, and one for I/O."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth???
No, that doesn't fit the description of what is going on.
In fact, your description doesn't seem to relate to VHDL at all.
I can't tell what you are talking about from this description,
but it sounds like it is for CPLDs, rather than FPGAs.
Rick C.
<clip>Ah, so he's bastardizing the term VHDL. (there's a little bit of Hugh in everyone)
They used it on a CPLD first, and on a Lattice FPGA 7k now. Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere it could probably be ported to
other FPGA families.
design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages,One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my
In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. InTrying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design,
that were true, why has nothing happened with it in the last six years?I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If
existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The
Each to their own. I've spent too much time on this, got to get back to work.Rick C.
Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.
I don't see a need for an exotic "Forth" front end (to generate what?).
\ Op Code File for MFX. Generated by MAKE-OPS v13in any equivalent part.
<clip>
The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work
<clip>
Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done
many, many times, some published, many not published. It would seem to be a trivial exercise.
Rick C.
Verilog, NOT VHDL. I found it to be too verbose.
And if you have a trivial solution to computer optimization, please post it!
(edited for clarity)
<clip>Designing logic with the Forth VHDL
1. Write a software simulation of the design. (Forth with local varables and a MAP extension)
2. Test the design. (test program, simple compiler and simulator written in Forth)
3. Convert the simulation into a hardware definition. (ED-MGEN, ED-CTRL, ED-DFRW, ED-DCDM, ED-DSEL)
4. Link instructions to modules. (EDIT-TRAN)
5. Compile the hardware definition into logic equations. (GEN-MAP, CTRL-MAP & DFRW-MAP programs}
6. Verify the logic equations work correctly. (EDIT-DISP, SIM-R32)
7. Assign the I/O pins. (ED-PINS, able to parse the csv pin file and combine it with the schematic foot print)
8. Fit the logic equations into the device. (Diamond from Lattice Semi does this, and there are universal ones)
9. Convert the routed design into a fusemap. (Diamond) 10. Compile the OS using the OP code definition file. (MAKE-OPS)
Our first CNC product had three 8032 processors. One for motion, One to process files, and one for I/O."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth???
No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
I can't tell what you are talking about from this description,
but it sounds like it is for CPLDs, rather than FPGAs.
Rick C.
We replaced the motion and file processors with the RACE, (Reduced Architecture Computation Engine)
in our new controller realased in 2000. The RACE and 4 motor controllers fit into a 1048 CPLD from Lattice.
In 2016 we moved the design to an X02-7000 and eliminated the 8032.
The design wasn't optomized for a LUT based part and the OS was getting too large for the address space
so it was obvious we needed to update the design.
Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
I've designed a wide variety of IP from servo system to networks and developed tools along to way to
assist in making such devices. For example the software from Lattice used for the RACE could only
achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
Designing and debuging the software for rapid processor evolution was more difficult than anticipated, asdesign additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages,
usual, but necessary for a reconfigurable product that could be used by small business having to compete
with large corporate monopolies that have gained control of the regulatory bodies and are using their
power to crush competion!
<clip>Ah, so he's bastardizing the term VHDL. (there's a little bit of Hugh in everyone)
They used it on a CPLD first, and on a Lattice FPGA 7k now. Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my
which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. InIn this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
<clip>
Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design,
that were true, why has nothing happened with it in the last six years?I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If
existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The
Each to their own. I've spent too much time on this, got to get back to work.Rick C.
Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.I don't know. You tell me.
I don't see a need for an exotic "Forth" front end (to generate what?).
\ Op Code File for MFX. Generated by MAKE-OPS v13in any equivalent part.
<clip>
The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work
<clip>design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages,
Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done
many, many times, some published, many not published. It would seem to be a trivial exercise.
Rick C.
Verilog, NOT VHDL. I found it to be too verbose.
And if you have a trivial solution to computer optimization, please post it!
(edited for clarity)
<clip>Designing logic with the Forth VHDL
1. Write a software simulation of the design. (Forth with local varables and a MAP extension)
2. Test the design. (test program, simple compiler and simulator written in Forth)
3. Convert the simulation into a hardware definition. (ED-MGEN, ED-CTRL, ED-DFRW, ED-DCDM, ED-DSEL)
4. Link instructions to modules. (EDIT-TRAN)
5. Compile the hardware definition into logic equations. (GEN-MAP, CTRL-MAP & DFRW-MAP programs}
6. Verify the logic equations work correctly. (EDIT-DISP, SIM-R32)
7. Assign the I/O pins. (ED-PINS, able to parse the csv pin file and combine it with the schematic foot print)
8. Fit the logic equations into the device. (Diamond from Lattice Semi does this, and there are universal ones)
9. Convert the routed design into a fusemap. (Diamond) 10. Compile the OS using the OP code definition file. (MAKE-OPS)
Our first CNC product had three 8032 processors. One for motion, One to process files, and one for I/O."Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth???
No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
I can't tell what you are talking about from this description,
but it sounds like it is for CPLDs, rather than FPGAs.
Rick C.
We replaced the motion and file processors with the RACE, (Reduced Architecture Computation Engine)
in our new controller realased in 2000. The RACE and 4 motor controllers fit into a 1048 CPLD from Lattice.
In 2016 we moved the design to an X02-7000 and eliminated the 8032.
The design wasn't optomized for a LUT based part and the OS was getting too large for the address space
so it was obvious we needed to update the design.
Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
I've designed a wide variety of IP from servo system to networks and developed tools along to way to
assist in making such devices. For example the software from Lattice used for the RACE could only
achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
Designing and debuging the software for rapid processor evolution was more difficult than anticipated, as
usual, but necessary for a reconfigurable product that could be used by small business having to compete
with large corporate monopolies that have gained control of the regulatory bodies and are using their
power to crush competion!
<clip>Ah, so he's bastardizing the term VHDL. (there's a little bit of Hugh in everyone)
They used it on a CPLD first, and on a Lattice FPGA 7k now. Hugh Aguilar was involved there.
And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.
One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my
which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. InIn this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
<clip>
Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design,
that were true, why has nothing happened with it in the last six years?I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If
existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The
Each to their own. I've spent too much time on this, got to get back to work.Rick C.
Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.I don't know. You tell me.
I don't see a need for an exotic "Forth" front end (to generate what?).
\ Op Code File for MFX. Generated by MAKE-OPS v13..
Each to their own. I've spent too much time on this, got to get back to work.
Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.I don't know. You tell me.
I don't see a need for an exotic "Forth" front end (to generate what?).
Please show us more as you have time.But to understand others aswell, that's the trick.
It reminds me somehow of how Forth started - as a tool for Chuck,
Here it is a tool for you and for Testra.
Chuck did not care about the opinion of others, still now does what he enjoys - and many do not understand.
On Sunday, October 16, 2022 at 4:22:36 PM UTC-4, johnro...@gmail.com wrote: <SNIP>
Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
I've designed a wide variety of IP from servo system to networks and developed tools along to way to
assist in making such devices. For example the software from Lattice used for the RACE could only
achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
Silicon is relatively inexpensive, these days. A project has to be very, very high volume to justify such an effort of optimization. I'm currently working
on a redesign because of component optimization and I'm happy with 100% overkill on a new part, because the chip cost is only $5 each. I could use a $3
part, but it is 4 kLUT and the previous design was using 90% of a 3 kLUT part. Since it is a change of not just family, but brand, I don't look forward to
spending excessive time shoehorning a design into a device. That makes alterations in the design prohibitively expensive as well.
Still, with a volume of perhaps 50,000 pieces, I might go with the smaller chip as long as I can share the footprint with the larger part.
--
Rick C.
In article <c1720c64-6805-4bf0...@googlegroups.com>,
Lorem Ipsum <gnuarm.del...@gmail.com> wrote:
On Sunday, October 16, 2022 at 4:22:36 PM UTC-4, johnro...@gmail.com wrote: <SNIP>
Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
I've designed a wide variety of IP from servo system to networks and developed tools along to way to
assist in making such devices. For example the software from Lattice used for the RACE could only
achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
Silicon is relatively inexpensive, these days. A project has to be very, very high volume to justify such an effort of optimization. I'm currently working
on a redesign because of component optimization and I'm happy with 100% overkill on a new part, because the chip cost is only $5 each. I could use a $3
part, but it is 4 kLUT and the previous design was using 90% of a 3 kLUT part. Since it is a change of not just family, but brand, I don't look forward to
spending excessive time shoehorning a design into a device. That makes alterations in the design prohibitively expensive as well.
Still, with a volume of perhaps 50,000 pieces, I might go with the smaller chip as long as I can share the footprint with the larger part.You overlook an important detail. The company doesn't save on silicon.
They create value based on proprietary silicon that can not easily be reverse engineered by others.
On Monday, October 17, 2022 at 7:26:26 AM UTC-4, none albert wrote:design?
In article <c1720c64-6805-4bf0...@googlegroups.com>,
Lorem Ipsum <gnuarm.del...@gmail.com> wrote:
On Sunday, October 16, 2022 at 4:22:36 PM UTC-4, johnro...@gmail.com wrote:<SNIP>
Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
I've designed a wide variety of IP from servo system to networks and developed tools along to way to
assist in making such devices. For example the software from Lattice used for the RACE could only
achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
Silicon is relatively inexpensive, these days. A project has to be very, very high volume to justify such an effort of optimization. I'm currently working
on a redesign because of component optimization and I'm happy with 100% overkill on a new part, because the chip cost is only $5 each. I could use a $3
part, but it is 4 kLUT and the previous design was using 90% of a 3 kLUT part. Since it is a change of not just family, but brand, I don't look forward to
spending excessive time shoehorning a design into a device. That makes alterations in the design prohibitively expensive as well.
You might want to define "easily". The bitstream for a number of Lattice devices has been reverse engineered to the point that there are open source tools that do not rely on any part of the Lattice tools. So how hard can it be to reverse engineer theStill, with a volume of perhaps 50,000 pieces, I might go with the smaller chip as long as I can share the footprint with the larger part.You overlook an important detail. The company doesn't save on silicon. They create value based on proprietary silicon that can not easily be reverse engineered by others.
"For example the software from Lattice used for the RACE could only achieve 80% ultization, I devised a tool that allowed us to achieve 100%,"give you the logic for free", meaning, it would be cost prohibitive to supply adequate routing to achieve 100% use of the logic for every design. Every design has different demands on the routing, so some users' designs are limited by the logic in an
I assume this meant he was trying to stay in a given size part. Regardless, I recall from the early days when users would complain to Xilinx that they could only use 90% of the logic in the device, that Xilinx would reply, "We sell you the routing and
I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accounts ofHugh's involvement.
--
Rick C.
+++ Get 1,000 miles of free Supercharging
+++ Tesla referral code - https://ts.la/richard11209
I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accountsof Hugh's involvement.
On 18/10/2022 12:47 am, Lorem Ipsum wrote:of Hugh's involvement.
I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accounts
I don't recall Hugh ever claiming involvement in the design of the chip (quite the opposite) but as he was employed to write software in support
of it, he would have gathered various info from the team that did. He's makes it clear his knowledge of the chip was second-hand:
https://groups.google.com/g/comp.lang.forth/c/moqYqLF64v8/m/BKuFAWlUfEYJ
On Monday, October 17, 2022 at 8:14:31 PM UTC-4, dxforth wrote:of Hugh's involvement.
On 18/10/2022 12:47 am, Lorem Ipsum wrote:
I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accounts
or even NO provocation at all. Reminds me of some other people here.I don't recall Hugh ever claiming involvement in the design of the chip (quite the opposite) but as he was employed to write software in support of it, he would have gathered various info from the team that did. He's makes it clear his knowledge of the chip was second-hand:
https://groups.google.com/g/comp.lang.forth/c/moqYqLF64v8/m/BKuFAWlUfEYJNo, I'm not saying Hugh was involved in designing the CPLD. He simply talked about it being designed. That's why I said I assume he had knowledge of it, but maybe not. It was hard to have a conversation with Hugh. He would go off his nut at very little
I remember trying to talk Hugh off a ledge a number of times, getting him to see that people here were not out to get him, it's just the way people are on the Internet sometimes. Again, reminds me of other people here. One in particular is obsessedwith righting wrongs or whatever, by stirring the pot himself in the name of "justice" and clearing his good name. I try not to respond to those people. It seldom is productive in any manner.
But this post is not really useful in this thread. I just wanted to clarify that I didn't think Hugh was directly involved in designing any of the hardware. Heck, from the conversations with him, it was clear that he had no knowledge of designing anysort of PLD. He did want to do something, but had no idea where to begin really, and would not accept any advice either.
--
Rick C.
But every garden has to be grown, not trampled because it's not somebody else's type of garden!
On 20/10/2022 12:36 am, Wayne morellini wrote:
But every garden has to be grown, not trampled because it's not somebody else's type of garden!The 'Steve' from this thread might be interested in being your gardener:
https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ
On 20/10/2022 11:52 pm, Wayne morellini wrote:
On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
On 20/10/2022 12:36 am, Wayne morellini wrote:
The 'Steve' from this thread might be interested in being your gardener: >>
But every garden has to be grown, not trampled because it's not somebody else's type of garden!
https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ
Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
All I saw was metaphors about growing gardens and not allowing others to trample it.
Face it, if we help each other, a lot more would get done.Perhaps c.l.f. doesn't need your help. It gets plenty of free offers as it
is - largely rejected, same as yours.
On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
On 20/10/2022 12:36 am, Wayne morellini wrote:
The 'Steve' from this thread might be interested in being your gardener:
But every garden has to be grown, not trampled because it's not somebody else's type of garden!
https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ
Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
Face it, if we help each other, a lot more would get done.
On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
On 20/10/2022 11:52 pm, Wayne morellini wrote:
On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
On 20/10/2022 12:36 am, Wayne morellini wrote:Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
The 'Steve' from this thread might be interested in being your gardener: >>>>
But every garden has to be grown, not trampled because it's not somebody else's type of garden!
https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ >>>
All I saw was metaphors about growing gardens and not allowing others to
trample it.
Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
Face it, if we help each other, a lot more would get done.Perhaps c.l.f. doesn't need your help. It gets plenty of free offers as it >> is - largely rejected, same as yours.
We were talking about helping one another in the context of helping somebody in particular. Look up Look up contrasting and context.
We simply don't need your help!
On 21/10/2022 2:10 pm, S wrote:
On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
On 20/10/2022 11:52 pm, Wayne morellini wrote:
On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
On 20/10/2022 12:36 am, Wayne morellini wrote:
Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
All I saw was metaphors about growing gardens and not allowing others to >> trample it.
Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.Identifying oneself with Hugh doesn't make for a great C.V. With the exception of
one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
at all. Often his own worst enemy, he burned every bridge he crossed.
Face it, if we help each other, a lot more would get done.Perhaps c.l.f. doesn't need your help. It gets plenty of free offers as it
is - largely rejected, same as yours.
We were talking about helping one another in the context of helping somebody in particular. Look up Look up contrasting and context.
We simply don't need your help!Look forward to the day you can say that to everyone.
On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
On 21/10/2022 2:10 pm, S wrote:
On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
On 20/10/2022 11:52 pm, Wayne morellini wrote:
On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote: >>>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
the better the human they are. I know plenty about themselves.Identifying oneself with Hugh doesn't make for a great C.V. With the exception ofNow, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
All I saw was metaphors about growing gardens and not allowing others to >>>> trample it.
Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
at all. Often his own worst enemy, he burned every bridge he crossed.
Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people,
On 21/10/2022 4:44 pm, S wrote:
On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
On 21/10/2022 2:10 pm, S wrote:
On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
On 20/10/2022 11:52 pm, Wayne morellini wrote:
On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote: >>>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
the better the human they are. I know plenty about themselves.Identifying oneself with Hugh doesn't make for a great C.V. With the exception ofNow, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
All I saw was metaphors about growing gardens and not allowing others to
trample it.
Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
at all. Often his own worst enemy, he burned every bridge he crossed.
Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people,
Yes, the value you place on people is boundless...
Sep 6, 2022, 10:07:48 PM
"But I, like many intelligent people, just leave them alone to their own delusions.
You can only help certain people."
Worthy of a Nobel Prize for humanity.
On Friday, 21 October 2022 at 8:27:18 pm UTC+10, dxforth wrote:the better the human they are. I know plenty about themselves.
On 21/10/2022 4:44 pm, S wrote:
On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
On 21/10/2022 2:10 pm, S wrote:
On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
On 20/10/2022 11:52 pm, Wayne morellini wrote:
On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote: >>>>>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
Identifying oneself with Hugh doesn't make for a great C.V. With the exception ofNow, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
All I saw was metaphors about growing gardens and not allowing others to >>>>>> trample it.
Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
at all. Often his own worst enemy, he burned every bridge he crossed.
Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people,
Yes, the value you place on people is boundless...
Sep 6, 2022, 10:07:48 PM
"But I, like many intelligent people, just leave them alone to their own delusions.
You can only help certain people."
Worthy of a Nobel Prize for humanity.
What are you quoting? But it is certain, you can only do so much, and some are too pathologically disrupted to be able to help further. Meaning they interfere, and will not listen. Moles and trolls.
I'm sorry if you have a need to follow people around, but I'm not interested. It may be good, if you stop derailing thread DX. The relevant side topics of how people have been addressed here have been addressed.
On 22/10/2022 9:34 am, S 1 wrote:the better the human they are. I know plenty about themselves.
On Friday, 21 October 2022 at 8:27:18 pm UTC+10, dxforth wrote:
On 21/10/2022 4:44 pm, S wrote:
On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
On 21/10/2022 2:10 pm, S wrote:
On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote: >>>>>> On 20/10/2022 11:52 pm, Wayne morellini wrote:
On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote: >>>>>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people,Identifying oneself with Hugh doesn't make for a great C.V. With the exception ofNow, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
All I saw was metaphors about growing gardens and not allowing others to
trample it.
Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
at all. Often his own worst enemy, he burned every bridge he crossed. >>>
What a nutty sentence. You got nothing to say a relevance,again, by the looks of it.Yes, the value you place on people is boundless...
Sep 6, 2022, 10:07:48 PM
"But I, like many intelligent people, just leave them alone to their own delusions.
You can only help certain people."
Worthy of a Nobel Prize for humanity.
What are you quoting? But it is certain, you can only do so much, and some are too pathologically disrupted to be able to help further. Meaning they interfere, and will not listen. Moles and trolls.
I'm sorry if you have a need to follow people around, but I'm not interested. It may be good, if you stop derailing thread DX. The relevant side topics of how people have been addressed here have been addressed.
I'm not responsible for your priorities - or lack thereof.
If you are jealous of people getting it right, maybe you should try being right instead? If you lack innovation, get some or shut up, stop going on like you are a jealous school girl!
On 23/10/2022 2:28 am, S 1 wrote:
If you are jealous of people getting it right, maybe you should try being right instead? If you lack innovation, get some or shut up, stop going on like you are a jealous school girl!
So what you have actually accomplished and of which others could rightly be jealous?
I haven't read all of your posts and it's possible I missed it among the accounts of
opportunities never realized and people that failed you. So, yes, please list your
accomplishments. It just may get you the help for which you constantly make appeal.
On Sunday, October 23, 2022 at 9:42:56 AM UTC+10, dxforth wrote:
On 23/10/2022 2:28 am, S 1 wrote:
If you are jealous of people getting it right, maybe you should try being right instead? If you lack innovation, get some or shut up, stop going on like you are a jealous school girl!
So what you have actually accomplished and of which others could rightly be jealous?
I haven't read all of your posts and it's possible I missed it among the accounts of
opportunities never realized and people that failed you. So, yes, please list your
accomplishments. It just may get you the help for which you constantly make appeal.
Unbelievable, you being a pest to people, you haven't read up, don't know what you are talking about, and have achieved nothing but pestering, and shifting around.
Thank you very much John - let's see what happens next.
Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote: <clip>
Thank you very much John - let's see what happens next.
Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
Finally getting close to finishing the development system and the processor.
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote: <clip>
Thank you very much John - let's see what happens next.
Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
Finally getting close to finishing the development system and the processor.
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
Just an idea:
I could convince Steve Teal to write the Minimum RISC in VHDL.
And as a bonus he added an eForth. https://github.com/Steve-Teal/eforth-misc16
How difficult would it be to replicate this design using your tools and Forth as VHDL?
And use the same FPGA you use now?
This would be a way to show others a full design,
using standard tools on one side,
and then compare it with your tools.
Your tools could then probably more easily show how to add additional IOs.
Thanks again - and can we have more please
Hugh appears to be stuck in a time loop, like Phill Connors in Ground Hogs Day.
His brother worked for us after he left on the HPGL converter, not Hugh. When he complained about it,
I explained that Tom was confused about that, and thought that would be the end of it.
Finally getting close to finishing the development system and the processor.
On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:<clip>
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obviousWhat additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your code.
Rick C.
I wrote MFX in 32-bit UR/Forth under a DOS-extender
in 1994. I was told that Testra had the sign an NDA for Ray Duncan in order to
obtain the UR/Forth source-code. Since that time, Testra has upgraded UR/Forth
to run under Windows, so they could continue to use UR/Forth all the way to 2023.
The NDA is still in effect. Testra can't distribute MFX or any of the other development
tools to anybody who doesn't also sign the NDA for Ray Duncan.
On Tuesday, 25 April 2023 at 18:13:11 UTC+1, John Hart wrote:
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
Thank you very much John - let's see what happens next.
Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
Finally getting close to finishing the development system and the processor.
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obviousLooking forward to more ...
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
And I just checked the dropbox link - still works.
I hope the formatting was helpful.
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:code.
On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:<clip>
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obviousWhat additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your
Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.
On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:code.
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:<clip>
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obviousWhat additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your
Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.
My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?
--
Rick C.
--+- Get 1,000 miles of free Supercharging
--+- Tesla referral code - https://ts.la/richard11209
On Tuesday, April 25, 2023 at 10:21:10 AM UTC-7, Jurgen Pitaske wrote:
On Tuesday, 25 April 2023 at 18:13:11 UTC+1, John Hart wrote:
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
Thank you very much John - let's see what happens next.
Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
Finally getting close to finishing the development system and the processor.
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obviousLooking forward to more ...
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
And I just checked the dropbox link - still works.
I hope the formatting was helpful.
I might provide the current instruction set in a more useful form after our product is finished, if there's any
interest. It's a universal 16 axis motion control system with two syncronized PWM outputs for laser, plasma,
3D printer, etc control.
After the processor is finished I was thinking about releasing the development tool in an open source format.
To perfect it will require a joint effort. Reconfigurable Processors have many advantages over fixed ones and
a variable instruction set could provide a level of security that would be very difficult to crack.
On Thursday, 27 April 2023 at 02:47:37 UTC+1, Lorem Ipsum wrote:your code.
On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:<clip>
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obviousWhat additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in
Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.
My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?
--
Rick C.
--+- Get 1,000 miles of free SuperchargingIt is not clear to anybody here why you are just adding useless noise here .
--+- Tesla referral code - https://ts.la/richard11209
If you do not know what CPLD / FPGA means
- there is a so called internet where you can find the information and understanding you are missing.
Or build your own.
In hardware
as CPLD for practice
Or in FPGA - here go to NandLand invest the money and start programming
or dig out the TTLs you should still have and build your own http://blog.notdot.net/2012/10/Build-your-own-FPGA
On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:code.
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:<clip>
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obviousWhat additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your
Not at all. Today FPGAs are better than PLDs for most everything, even small jobs. Our PLD based processer was written in Forth and mapped directly into logic equations that fit the format of the PLD. When we moved the design to the FPGA theRick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.
My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?
Rick C.
On Thursday, April 27, 2023 at 2:18:16 AM UTC-4, Jurgen Pitaske wrote:your code.
On Thursday, 27 April 2023 at 02:47:37 UTC+1, Lorem Ipsum wrote:
On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:<clip>
On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obviousWhat additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.
I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in
Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.
My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?
--
Rick C.
--+- Get 1,000 miles of free SuperchargingIt is not clear to anybody here why you are just adding useless noise here .
--+- Tesla referral code - https://ts.la/richard11209
If you do not know what CPLD / FPGA meansThank you for your kind words of support and encouragement. Everyone says how marvelous it is that we have you to guide us and teach us.
- there is a so called internet where you can find the information and understanding you are missing.
Or build your own.
In hardware
as CPLD for practice
Or in FPGA - here go to NandLand invest the money and start programming
or dig out the TTLs you should still have and build your own http://blog.notdot.net/2012/10/Build-your-own-FPGA
I feel wiser, just having read your remarks.
--
Rick C.
--++ Get 1,000 miles of free Supercharging
--++ Tesla referral code - https://ts.la/richard11209
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations.
FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential
operations in your code.
Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.
The basic logic unit of a CPGA has 16 to 20 inputs.
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
only 4 to 20.
On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
I can't think of anything that is harder to do in an FPGA than in a CPLD,
unless CPLDs have something akin to "long lines" which FPGAs used to use,
until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations.
FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential
operations in your code.
Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
The basic logic unit of a CPGA has 16 to 20 inputs.
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
only 4 to 20.
This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.
Rick Collins is a clown because he doesn't understand this. He says that a VLIW
is easy on an FPGA, although he has never done this. He's fantasizing.
The strength of an FPGA is that they "are the embodiment of parallel operations."
This has to be loosely-coupled parallelism to avoid the connectivity problem.
This is why all modern FPGA designs are multi-core systems.
John Hart is a clown because he doesn't because he doesn't understand this. He says
that his single-core RACE processor is relevant in modern times, but it isn't.
The MiniForth was pretty awesome in 1995 when it came out.
If I had continued building upon MFX I could have made it successful, at least for a while.
A VLIW processor is obsolete now (this might still be possible in an ASIC, though).
The truth that John Hart dodges is that I did write MFX.
He contributed only bad advice that I ignored (he expected the application programmer
to do the out-of-ordering, but I wrote MFX to do this automatically).
I was being a team player by succeeding at writing MFX despite the abysmally low pay,
lack of health insurance and lack of support (no advice whatsoever on how to do this).
Testra totally betrayed me by refusing to admit that I wrote MFX, telling everybody that
I was a stupid little maintenance programmer who pretends to have written MFX that I used
but that real programmers (John Hart and Steve Brault) actually wrote. Nobody will ever hire a liar!
Nobody should hire Testra because Tom Hart and John Hart are liars.
The problem is not just that their single-core processor is obsolete in the 21st century,
the problem is that they betrayed their employee in 1995, and continue to do this today.
Nobody will ever agree to be their employee when the result is certain betrayal.
Nobody should hire Testra because Tom Hart and John Hart are liars.
On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
I can't think of anything that is harder to do in an FPGA than in a CPLD,
unless CPLDs have something akin to "long lines" which FPGAs used to use,
until they grew out of them with logic being faster.
There is nothing about FPGAs to preclude or make harder parallel operations.
FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential
operations in your code.
Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
The basic logic unit of a CPGA has 16 to 20 inputs.
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
only 4 to 20.
This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.
Rick Collins is a clown because he doesn't understand this. He says that a VLIW
is easy on an FPGA, although he has never done this. He's fantasizing.
The strength of an FPGA is that they "are the embodiment of parallel operations."
This has to be loosely-coupled parallelism to avoid the connectivity problem.
This is why all modern FPGA designs are multi-core systems.
John Hart is a clown because he doesn't because he doesn't understand this. He says
that his single-core RACE processor is relevant in modern times, but it isn't.
The MiniForth was pretty awesome in 1995 when it came out.
If I had continued building upon MFX I could have made it successful, at least for a while.
A VLIW processor is obsolete now (this might still be possible in an ASIC, though).
The truth that John Hart dodges is that I did write MFX.
He contributed only bad advice that I ignored (he expected the application programmer
to do the out-of-ordering, but I wrote MFX to do this automatically).
I was being a team player by succeeding at writing MFX despite the abysmally low pay,
lack of health insurance and lack of support (no advice whatsoever on how to do this).
Testra totally betrayed me by refusing to admit that I wrote MFX, telling everybody that
I was a stupid little maintenance programmer who pretends to have written MFX that I used
but that real programmers (John Hart and Steve Brault) actually wrote. Nobody will ever hire a liar!
Nobody should hire Testra because Tom Hart and John Hart are liars.
The problem is not just that their single-core processor is obsolete in the 21st century,
the problem is that they betrayed their employee in 1995, and continue to do this today.
Nobody will ever agree to be their employee when the result is certain betrayal.
On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:<clip>
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
I can't think of anything that is harder to do in an FPGA than in a CPLD,
<clip>There is nothing about FPGAs to preclude or make harder parallel operations.
Not true!Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
The basic logic unit of a CPGA has 16 to 20 inputs.
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
only 4 to 20.
This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.I don't know what a VLIW is, but I know anything possible on a PLD can be done better on a modern FPGA.
A VLIW processor is obsolete now (this might still be possible in an ASIC, though).
On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:
On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:<clip>
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
I can't think of anything that is harder to do in an FPGA than in a CPLD,
<clip>There is nothing about FPGAs to preclude or make harder parallel operations.
Rick C.
Not true!The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
The basic logic unit of a CPGA has 16 to 20 inputs.
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
only 4 to 20.
This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.I don't know what a VLIW is, but I know anything possible on a PLD can be done better on a modern FPGA.
<ad hominem & nonsense clipped>
A VLIW processor is obsolete now (this might still be possible in an ASIC, though).Our original MSI LSI based processor (4S32) used in thousands ofTicketMaster terminals,
was a Harvard architecture with a 32 bit instruction (not sure if that qualifies as VLIW),
a 16 bit data path and 4 bit ALU. [An emulation of an Intel 286 (virtual PC) on it would
run a little faster than it. An emulation of a customers 16 bit processor ran 5 times faster.]
The Forth multi-user system we manufactured using the same CPU supported 7 users.
When we moved the design to the PLD ,the instruction width was shrunk to 16 bits, which
I'm sure doesn't qualify as a Very Large Instruction Width. The arithmetic part of the ALU
remained 4 bits but the logic part became 16.
The instruction word for the RACE32 is 18 bits, so it's not a VLIW either, but the ALU and internal data path have been expanded to 32 bits, enabled by the fast ripple carry feature of FPGAs.
The power of modern FPGA would blow people's minds, if they understood them. Advanced supercomputer have tens of thousands of chips with thousands of processes
running in each one with more computing power than a PC. The fear about AAI taking
over the world is based on the reality of what can be done with this power and how dangerous it would be if abused.
Restrictions won't reduce the danger, they'll make it more dangerous, more concentrated.
The solution to Big Tech having too much power is to empower people. Enable small business
to use robotics and automation to compete. Something like an open source platform programed
in Forth for automation would be the ideal tool to enable it. Focusing on solutions is the
only way out of the mess we're in, Attacks and flame wars are a DEAD END, they accomplish
NOTHING, and the din drowns out rational discourse.
HUGH WROTE MFX, never said he didn't. He was quite creative at the time.
<clip more ad hominem crap>
On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:
On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:<clip>
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
I can't think of anything that is harder to do in an FPGA than in a CPLD,
<clip>There is nothing about FPGAs to preclude or make harder parallel operations.
Rick C.
Not true!The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
The basic logic unit of a CPGA has 16 to 20 inputs.
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
only 4 to 20.
This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.I don't know what a VLIW is, but I know anything possible on a PLD can be done better on a modern FPGA.
The power of modern FPGA would blow people's minds, if they understood them. Advanced supercomputer have tens of thousands of chips with thousands of processes
running in each one with more computing power than a PC. The fear about AAI taking
over the world is based on the reality of what can be done with this power and how dangerous it would be if abused.
HUGH WROTE MFX, never said he didn't. He was quite creative at the time.
The official answer from Tom Hart, their president,
who agreed to have his answer to me published on clf:
+++++++++++++++++++++++++++++++++++++++++++++++++++++++
[Hugh] wrote our Forth compiler for the processor
that we implemented in a Lattice PLD.
He did a good job on it,
we are still using it with a few bug fixes and minor modifications.
He had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long before
we ever ran across Hugh.
Why did Testra attack me on comp.lang.forth with lies and insults?
Tom Hart made this attack on the command of Juergen Pintaske, the MPE salesman.
Apparently you were in negotiation with Stephen Pelc for him to buy the RACE processor,
and you believed that you had to obey Juergen Pintaske's commands to stay on Stephen Pelc's good side. It is unlikely that Stephen Pelc was going to buy your RACE
processor. He was most likely just tugging your chain for the entertainment value of
getting you to attack your own employee on comp.lang.forth. You think that you can
totally crush me here on comp.lang.forth, but you harm yourself as much or more
than you harm me. Testra won't be considered to be a reputable company any more.
You have more to lose than I do. People who live in glass houses shouldn't throw stones!
Attacking me on comp.lang.forth was a bad idea. Was alcohol involved in this decision?
Why did Testra attack me on comp.lang.forth with lies and insults?
I had just asked Testra to kindly state his activities with Testra
On Friday, April 28, 2023 at 2:56:23 PM UTC-4, John Hart wrote:Not your fault if you still rely on MSM for your news.
On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:
On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
I can't think of anything that is harder to do in an FPGA than in a CPLD,
<clip>
What mess??? I must have missed something.
Rick C.
On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
No one from Testra ever attacked anyone on comp.lang.forthWhy did Testra attack me on comp.lang.forth with lies and insults?
or any other news group ever.
A gifted programmer, with no experience was given a chance,
succeeded and was let go after he finished because there was
nothing for him to do.
I had just asked Testra to kindly state his activities with TestraWhich indicated he was a creative individual and like many creative individuals, might be difficult to work with. A truth that's easily verified by reading posts on this and many other tech newsgroups.
Not referring to anyone specific, some people not only burn their bridges they spend years taking the foundation down to bedrock with a jackhammer until no evidence of what they accomplished remains.
Flame wars are not only counterproductive they're destructive. Most
people, if they knew then what they know now, would have done things differently. It's also true that if wishes were horses, beggers would ride.
Learning from past mistakes is good, getting mired in them is not.
My purpose for writing is NOT to get sucked into a flame war,
it's to have a discussion about Forth being the ideal language for a Reconfigurable Architecture Computation Engine, specifically the
RACE32, which we are in the process of completing,
A thousand such processors could run on one of the new FPGA chips,
but the main applications, automation and robotics, would require
only one and run on a low cost device.
jrh
On Friday, April 28, 2023 at 5:06:51 PM UTC-7, Lorem Ipsum wrote:
On Friday, April 28, 2023 at 2:56:23 PM UTC-4, John Hart wrote:Not your fault if you still rely on MSM for your news.
On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:What mess??? I must have missed something.
On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
I can't think of anything that is harder to do in an FPGA than in a CPLD,
<clip>
Rick C.
America is in sharp decline on many fronts and MSM has been working overtime hiding it. The parts of our social economic system are strongly linked and
a series of errors by the current administration, as serious as the Titanic hittting an iceberg, have occured. The only solution is to get productivity growing faster than debt to prevent runaway inflation, and that's going
to require an autiomation revolution at the roots. The concentration of wealth by the Elite, not only stifles innovation it's extremely dangerous. After all, power corrupts and absolute power corrupts absolutely.
On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
No one from Testra ever attacked anyone on comp.lang.forthWhy did Testra attack me on comp.lang.forth with lies and insults?
or any other news group ever.
I let him go myself,
after I had given him a project to write a DXF converter to HPGL code.
He would not take any direction.
I scrapped the project.
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long before
we ever ran across Hugh.
No one from Testra ever attacked anyone on comp.lang.forthBullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
or any other news group ever.
Not referring to anyone specific, some people not only burn their bridges they spend years taking the foundation down to bedrock with a jackhammer until no evidence of what they accomplished remains.
On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
Bullshit!No one from Testra ever attacked anyone on comp.lang.forthWhy did Testra attack me on comp.lang.forth with lies and insults?
or any other news group ever.
This entire thread was an unprovoked attack on me: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
Tom Hart was totally lying:
I let him go myself,
after I had given him a project to write a DXF converter to HPGL code.
He would not take any direction.
I scrapped the project.
I never even heard of HPGL before this attack. There was no HPGL project. Also, I never got any direction in any of my work.
When I wrote the DXF to GCODE converter nobody told me about how
Bezier Splines might work. I didn't know about Bezier Splines, and I assume that the reason I wasn't told about Bezier Splines is that Tom and John Hart don't know about them either. Tom Hart would just angrily tell me:
"Just make a smooth line through all the tiny line segments!"
There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
weren't touching any other line segment and some touched other line segments.
I had no idea how to make a smooth line through this mess. I wished that I did
have some direction, but I never did. I wished that I had mind-reading ability
so that I could know what image the artist had intended with this mish-mash. Tom Hart says that I'm too stupid to write a data-conversion program.
This isn't true. I was converting DXF code to GCODE within a couple of weeks of starting the project. The problem was that the result was a mess.
When I started the project I was told that this was a simple data-conversion program, so I felt confident that I could finish in a few weeks. If I had been told
that I had to make a smooth line through a big mess of tiny line-segments,
I would have refused the job. If I had been told that I needed Bezier Splines
I would have refused the job because I don't know anything about the subject.
(This is where the comp.lang.forth trolls can spring into action and say that
they could easily implement Bezier Splines, so they get to be big internet experts
without writing any code, as usual).
Tom Hart was totally lying:
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long before we ever ran across Hugh.The original Forth Engine was a bit-slice processor.
This is unrelated to the MiniForth that was a VLIW processor.
Tom Hart is saying that MFX was written for the bit-slice processor and then was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
All of that was written by John Perona who later wrote Multi-Edit. Even if there
had been some similarity between the original Forth Engine and the MiniForth,
I still wouldn't have looked at John Perona's code because I never look at other
people's code (that is like peering through a bedroom window to look at your neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
who writes multi-page functions. He doesn't factor code at all.
Testra was originally called Hartronics and they advertised their "Forth Engine"
in Forth Dimensions, in case anybody cares (I don't).
It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
attacks on me over the last four years have been based on him obtaining 100% support from Tom Hart.
It is very disingenuous for John Hart to now say:
No one from Testra ever attacked anyone on comp.lang.forthBullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
or any other news group ever.
Instead you provided Juergen Pintaske with 100% support for attacking me. Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
Not referring to anyone specific, some people not only burn their bridges they spend years taking the foundation down to bedrock with a jackhammer until no evidence of what they accomplished remains.It was in the 1990s, less than five years after I left Testra, when I heard John Hart
(possibly Tom Hart doing an impersonation) say on speaker-phone that I had accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
been saying this starting immediately after I left Testra but it was a few years later
when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
Tom Hart cares about loyalty! He expects employees to remain employed forever,
never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
Tom Hart has no sense of loyalty to his employees and will attack them in public.
Why didn't Testra just tell me when I left that leaving was an act of disloyalty
and that I would never get a reference? I made a fool out of myself by going to
job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
Most likely, Testra wanted me to go to these job interviews and describe MFX,
not for my benefit, but just as an advertisement for Testra's MiniForth processor.
They may have been hoping that Lockheed Martin would buy the MiniForth so they could become wealthy, but they had no way to get Lockheed Martin's attention.
You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
"Hi! I've got a super-awesome processor! Would you like to buy it?"
They may have believed (correctly) that for me to go to a job interview at Lockheed Martin and describe MFX would be the only way that Lockheed Martin would find out about the MiniForth --- but they would pull the rug out from under me
by telling Lockheed Martin that they wrote MFX --- they would explain to Lockheed Martin that they are geniuses who deserve to get rich!
On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
Bullshit!No one from Testra ever attacked anyone on comp.lang.forthWhy did Testra attack me on comp.lang.forth with lies and insults?
or any other news group ever.
This entire thread was an unprovoked attack on me: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
Tom Hart was totally lying:
I let him go myself,
after I had given him a project to write a DXF converter to HPGL code. He would not take any direction.
I scrapped the project.
I never even heard of HPGL before this attack. There was no HPGL project. Also, I never got any direction in any of my work.
When I wrote the DXF to GCODE converter nobody told me about how
Bezier Splines might work. I didn't know about Bezier Splines, and I assume
that the reason I wasn't told about Bezier Splines is that Tom and John Hart
don't know about them either. Tom Hart would just angrily tell me:
"Just make a smooth line through all the tiny line segments!"
There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
weren't touching any other line segment and some touched other line segments.
I had no idea how to make a smooth line through this mess. I wished that I did
have some direction, but I never did. I wished that I had mind-reading ability
so that I could know what image the artist had intended with this mish-mash.
Tom Hart says that I'm too stupid to write a data-conversion program.
This isn't true. I was converting DXF code to GCODE within a couple of weeks
of starting the project. The problem was that the result was a mess.
When I started the project I was told that this was a simple data-conversion
program, so I felt confident that I could finish in a few weeks. If I had been told
that I had to make a smooth line through a big mess of tiny line-segments, I would have refused the job. If I had been told that I needed Bezier Splines
I would have refused the job because I don't know anything about the subject.
(This is where the comp.lang.forth trolls can spring into action and say that
they could easily implement Bezier Splines, so they get to be big internet experts
without writing any code, as usual).
Tom Hart was totally lying:
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long beforeThe original Forth Engine was a bit-slice processor.
we ever ran across Hugh.
This is unrelated to the MiniForth that was a VLIW processor.
Tom Hart is saying that MFX was written for the bit-slice processor and then
was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
All of that was written by John Perona who later wrote Multi-Edit. Even if there
had been some similarity between the original Forth Engine and the MiniForth,
I still wouldn't have looked at John Perona's code because I never look at other
people's code (that is like peering through a bedroom window to look at your
neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
who writes multi-page functions. He doesn't factor code at all.
Testra was originally called Hartronics and they advertised their "Forth Engine"
in Forth Dimensions, in case anybody cares (I don't).
It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
attacks on me over the last four years have been based on him obtaining 100%
support from Tom Hart.
It is very disingenuous for John Hart to now say:
No one from Testra ever attacked anyone on comp.lang.forthBullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
or any other news group ever.
Instead you provided Juergen Pintaske with 100% support for attacking me. Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
Not referring to anyone specific, some people not only burn their bridgesIt was in the 1990s, less than five years after I left Testra, when I heard John Hart
they spend years taking the foundation down to bedrock with a jackhammer until no evidence of what they accomplished remains.
(possibly Tom Hart doing an impersonation) say on speaker-phone that I had accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
been saying this starting immediately after I left Testra but it was a few years later
when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
Tom Hart cares about loyalty! He expects employees to remain employed forever,
never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
Tom Hart has no sense of loyalty to his employees and will attack them in public.
Why didn't Testra just tell me when I left that leaving was an act of disloyaltyWHAT A MENTAL DESASTER AGAIN.
and that I would never get a reference? I made a fool out of myself by going to
job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
Most likely, Testra wanted me to go to these job interviews and describe MFX,
not for my benefit, but just as an advertisement for Testra's MiniForth processor.
They may have been hoping that Lockheed Martin would buy the MiniForth so they could become wealthy, but they had no way to get Lockheed Martin's attention.
You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
"Hi! I've got a super-awesome processor! Would you like to buy it?"
They may have believed (correctly) that for me to go to a job interview at Lockheed Martin and describe MFX would be the only way that Lockheed Martin
would find out about the MiniForth --- but they would pull the rug out from under me
by telling Lockheed Martin that they wrote MFX --- they would explain to Lockheed Martin that they are geniuses who deserve to get rich!
Everybody is a liar - which automatically leads to
HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
GO BACK TO YOUR CAGE AND BARK OR NOT.
Another made up piece of lies - just to make you feel good.
I did my job at MPE as consultant,
which triggered tmy FORTH BOOKSHELF on amazon https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
What have you contributed over the last 30 years
- except of often dayly rants and
accusations of probably everybody here.
On Sunday, 30 April 2023 at 07:14:16 UTC+1, Jurgen Pitaske wrote:
On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
Bullshit!No one from Testra ever attacked anyone on comp.lang.forthWhy did Testra attack me on comp.lang.forth with lies and insults?
or any other news group ever.
This entire thread was an unprovoked attack on me: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
Tom Hart was totally lying:
I let him go myself,
after I had given him a project to write a DXF converter to HPGL code. He would not take any direction.
I scrapped the project.
I never even heard of HPGL before this attack. There was no HPGL project.
Also, I never got any direction in any of my work.
When I wrote the DXF to GCODE converter nobody told me about how
Bezier Splines might work. I didn't know about Bezier Splines, and I assume
that the reason I wasn't told about Bezier Splines is that Tom and John Hart
don't know about them either. Tom Hart would just angrily tell me:
"Just make a smooth line through all the tiny line segments!"
There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
weren't touching any other line segment and some touched other line segments.
I had no idea how to make a smooth line through this mess. I wished that I did
have some direction, but I never did. I wished that I had mind-reading ability
so that I could know what image the artist had intended with this mish-mash.
Tom Hart says that I'm too stupid to write a data-conversion program. This isn't true. I was converting DXF code to GCODE within a couple of weeks
of starting the project. The problem was that the result was a mess. When I started the project I was told that this was a simple data-conversion
program, so I felt confident that I could finish in a few weeks. If I had been told
that I had to make a smooth line through a big mess of tiny line-segments,
I would have refused the job. If I had been told that I needed Bezier Splines
I would have refused the job because I don't know anything about the subject.
(This is where the comp.lang.forth trolls can spring into action and say that
they could easily implement Bezier Splines, so they get to be big internet experts
without writing any code, as usual).
Tom Hart was totally lying:
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long beforeThe original Forth Engine was a bit-slice processor.
we ever ran across Hugh.
This is unrelated to the MiniForth that was a VLIW processor.
Tom Hart is saying that MFX was written for the bit-slice processor and then
was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
All of that was written by John Perona who later wrote Multi-Edit. Even if there
had been some similarity between the original Forth Engine and the MiniForth,
I still wouldn't have looked at John Perona's code because I never look at other
people's code (that is like peering through a bedroom window to look at your
neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
who writes multi-page functions. He doesn't factor code at all.
Testra was originally called Hartronics and they advertised their "Forth Engine"
in Forth Dimensions, in case anybody cares (I don't).
It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
attacks on me over the last four years have been based on him obtaining 100%
support from Tom Hart.
It is very disingenuous for John Hart to now say:
No one from Testra ever attacked anyone on comp.lang.forthBullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
or any other news group ever.
Instead you provided Juergen Pintaske with 100% support for attacking me.
Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
Not referring to anyone specific, some people not only burn their bridgesIt was in the 1990s, less than five years after I left Testra, when I heard John Hart
they spend years taking the foundation down to bedrock with a jackhammer
until no evidence of what they accomplished remains.
(possibly Tom Hart doing an impersonation) say on speaker-phone that I had
accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
been saying this starting immediately after I left Testra but it was a few years later
when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
Tom Hart cares about loyalty! He expects employees to remain employed forever,
never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
Tom Hart has no sense of loyalty to his employees and will attack them in public.
Why didn't Testra just tell me when I left that leaving was an act of disloyaltyWHAT A MENTAL DESASTER AGAIN.
and that I would never get a reference? I made a fool out of myself by going to
job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
Most likely, Testra wanted me to go to these job interviews and describe MFX,
not for my benefit, but just as an advertisement for Testra's MiniForth processor.
They may have been hoping that Lockheed Martin would buy the MiniForth so
they could become wealthy, but they had no way to get Lockheed Martin's attention.
You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
"Hi! I've got a super-awesome processor! Would you like to buy it?"
They may have believed (correctly) that for me to go to a job interview at
Lockheed Martin and describe MFX would be the only way that Lockheed Martin
would find out about the MiniForth --- but they would pull the rug out from under me
by telling Lockheed Martin that they wrote MFX --- they would explain to Lockheed Martin that they are geniuses who deserve to get rich!
Everybody is a liar - which automatically leads to
HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
GO BACK TO YOUR CAGE AND BARK OR NOT.
Another made up piece of lies - just to make you feel good.
I did my job at MPE as consultant,LIAR LIAR LIAR - YOU ARE DOING WELL.
which triggered tmy FORTH BOOKSHELF on amazon https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
What have you contributed over the last 30 years
- except of often dayly rants and
accusations of probably everybody here.
To state that my letter to Testra and the kind answer from there was started without reason
is the biggest lie you ever told.
You have attacked me over the last 10 years for no real reason
- it is all here on CLF so you can check
for no real reason.
So I wondered what Testra would say about you,
and it ended up in the probably most read post of CLF with about 4400 reads now.
https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
It will be 4444 soon -
You cannot get closer to fours.
Have a nice day,
and May The Fours Be With You.
On Sunday, 30 April 2023 at 07:14:16 UTC+1, Jurgen Pitaske wrote:
On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
Bullshit!No one from Testra ever attacked anyone on comp.lang.forthWhy did Testra attack me on comp.lang.forth with lies and insults?
or any other news group ever.
This entire thread was an unprovoked attack on me: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
Tom Hart was totally lying:
I let him go myself,
after I had given him a project to write a DXF converter to HPGL code. He would not take any direction.
I scrapped the project.
I never even heard of HPGL before this attack. There was no HPGL project.
Also, I never got any direction in any of my work.
When I wrote the DXF to GCODE converter nobody told me about how
Bezier Splines might work. I didn't know about Bezier Splines, and I assume
that the reason I wasn't told about Bezier Splines is that Tom and John Hart
don't know about them either. Tom Hart would just angrily tell me:
"Just make a smooth line through all the tiny line segments!"
There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
weren't touching any other line segment and some touched other line segments.
I had no idea how to make a smooth line through this mess. I wished that I did
have some direction, but I never did. I wished that I had mind-reading ability
so that I could know what image the artist had intended with this mish-mash.
Tom Hart says that I'm too stupid to write a data-conversion program. This isn't true. I was converting DXF code to GCODE within a couple of weeks
of starting the project. The problem was that the result was a mess. When I started the project I was told that this was a simple data-conversion
program, so I felt confident that I could finish in a few weeks. If I had been told
that I had to make a smooth line through a big mess of tiny line-segments,
I would have refused the job. If I had been told that I needed Bezier Splines
I would have refused the job because I don't know anything about the subject.
(This is where the comp.lang.forth trolls can spring into action and say that
they could easily implement Bezier Splines, so they get to be big internet experts
without writing any code, as usual).
Tom Hart was totally lying:
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long beforeThe original Forth Engine was a bit-slice processor.
we ever ran across Hugh.
This is unrelated to the MiniForth that was a VLIW processor.
Tom Hart is saying that MFX was written for the bit-slice processor and then
was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
All of that was written by John Perona who later wrote Multi-Edit. Even if there
had been some similarity between the original Forth Engine and the MiniForth,
I still wouldn't have looked at John Perona's code because I never look at other
people's code (that is like peering through a bedroom window to look at your
neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
who writes multi-page functions. He doesn't factor code at all.
Testra was originally called Hartronics and they advertised their "Forth Engine"
in Forth Dimensions, in case anybody cares (I don't).
It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
attacks on me over the last four years have been based on him obtaining 100%
support from Tom Hart.
It is very disingenuous for John Hart to now say:
No one from Testra ever attacked anyone on comp.lang.forthBullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
or any other news group ever.
Instead you provided Juergen Pintaske with 100% support for attacking me.
Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
Not referring to anyone specific, some people not only burn their bridgesIt was in the 1990s, less than five years after I left Testra, when I heard John Hart
they spend years taking the foundation down to bedrock with a jackhammer
until no evidence of what they accomplished remains.
(possibly Tom Hart doing an impersonation) say on speaker-phone that I had
accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
been saying this starting immediately after I left Testra but it was a few years later
when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
Tom Hart cares about loyalty! He expects employees to remain employed forever,
never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
Tom Hart has no sense of loyalty to his employees and will attack them in public.
Why didn't Testra just tell me when I left that leaving was an act of disloyaltyWHAT A MENTAL DESASTER AGAIN.
and that I would never get a reference? I made a fool out of myself by going to
job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
Most likely, Testra wanted me to go to these job interviews and describe MFX,
not for my benefit, but just as an advertisement for Testra's MiniForth processor.
They may have been hoping that Lockheed Martin would buy the MiniForth so
they could become wealthy, but they had no way to get Lockheed Martin's attention.
You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
"Hi! I've got a super-awesome processor! Would you like to buy it?"
They may have believed (correctly) that for me to go to a job interview at
Lockheed Martin and describe MFX would be the only way that Lockheed Martin
would find out about the MiniForth --- but they would pull the rug out from under me
by telling Lockheed Martin that they wrote MFX --- they would explain to Lockheed Martin that they are geniuses who deserve to get rich!
Everybody is a liar - which automatically leads to
HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
GO BACK TO YOUR CAGE AND BARK OR NOT.
Another made up piece of lies - just to make you feel good.
I did my job at MPE as consultant,LIAR LIAR LIAR - YOU ARE DOING WELL.
which triggered tmy FORTH BOOKSHELF on amazon https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
What have you contributed over the last 30 years
- except of often dayly rants and
accusations of probably everybody here.
To state that my letter to Testra and the kind answer from there was started without reason
is the biggest lie you ever told.
You have attacked me over the last 10 years for no real reason
- it is all here on CLF so you can check
for no real reason.
So I wondered what Testra would say about you,
and it ended up in the probably most read post of CLF with about 4400 reads now.
https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
It will be 4444 soon -
You cannot get closer to fours.
Have a nice day,
and May The Fours Be With You.
On Sunday, 30 April 2023 at 07:22:12 UTC+1, Jurgen Pitaske wrote:
On Sunday, 30 April 2023 at 07:14:16 UTC+1, Jurgen Pitaske wrote:
On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
Bullshit!No one from Testra ever attacked anyone on comp.lang.forthWhy did Testra attack me on comp.lang.forth with lies and insults?
or any other news group ever.
This entire thread was an unprovoked attack on me: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
Tom Hart was totally lying:
I let him go myself,
after I had given him a project to write a DXF converter to HPGL code.
He would not take any direction.
I scrapped the project.
I never even heard of HPGL before this attack. There was no HPGL project.
Also, I never got any direction in any of my work.
When I wrote the DXF to GCODE converter nobody told me about how Bezier Splines might work. I didn't know about Bezier Splines, and I assume
that the reason I wasn't told about Bezier Splines is that Tom and John Hart
don't know about them either. Tom Hart would just angrily tell me: "Just make a smooth line through all the tiny line segments!"
There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
weren't touching any other line segment and some touched other line segments.
I had no idea how to make a smooth line through this mess. I wished that I did
have some direction, but I never did. I wished that I had mind-reading ability
so that I could know what image the artist had intended with this mish-mash.
Tom Hart says that I'm too stupid to write a data-conversion program. This isn't true. I was converting DXF code to GCODE within a couple of weeks
of starting the project. The problem was that the result was a mess. When I started the project I was told that this was a simple data-conversion
program, so I felt confident that I could finish in a few weeks. If I had been told
that I had to make a smooth line through a big mess of tiny line-segments,
I would have refused the job. If I had been told that I needed Bezier Splines
I would have refused the job because I don't know anything about the subject.
(This is where the comp.lang.forth trolls can spring into action and say that
they could easily implement Bezier Splines, so they get to be big internet experts
without writing any code, as usual).
Tom Hart was totally lying:
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long beforeThe original Forth Engine was a bit-slice processor.
we ever ran across Hugh.
This is unrelated to the MiniForth that was a VLIW processor.
Tom Hart is saying that MFX was written for the bit-slice processor and then
was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
All of that was written by John Perona who later wrote Multi-Edit. Even if there
had been some similarity between the original Forth Engine and the MiniForth,
I still wouldn't have looked at John Perona's code because I never look at other
people's code (that is like peering through a bedroom window to look at your
neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
who writes multi-page functions. He doesn't factor code at all.
Testra was originally called Hartronics and they advertised their "Forth Engine"
in Forth Dimensions, in case anybody cares (I don't).
It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
attacks on me over the last four years have been based on him obtaining 100%
support from Tom Hart.
It is very disingenuous for John Hart to now say:
No one from Testra ever attacked anyone on comp.lang.forthBullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
or any other news group ever.
Instead you provided Juergen Pintaske with 100% support for attacking me.
Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
Not referring to anyone specific, some people not only burn their bridgesIt was in the 1990s, less than five years after I left Testra, when I heard John Hart
they spend years taking the foundation down to bedrock with a jackhammer
until no evidence of what they accomplished remains.
(possibly Tom Hart doing an impersonation) say on speaker-phone that I had
accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
been saying this starting immediately after I left Testra but it was a few years later
when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
Tom Hart cares about loyalty! He expects employees to remain employed forever,
never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
Tom Hart has no sense of loyalty to his employees and will attack them in public.
Why didn't Testra just tell me when I left that leaving was an act of disloyaltyWHAT A MENTAL DESASTER AGAIN.
and that I would never get a reference? I made a fool out of myself by going to
job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
Most likely, Testra wanted me to go to these job interviews and describe MFX,
not for my benefit, but just as an advertisement for Testra's MiniForth processor.
They may have been hoping that Lockheed Martin would buy the MiniForth so
they could become wealthy, but they had no way to get Lockheed Martin's attention.
You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
"Hi! I've got a super-awesome processor! Would you like to buy it?" They may have believed (correctly) that for me to go to a job interview at
Lockheed Martin and describe MFX would be the only way that Lockheed Martin
would find out about the MiniForth --- but they would pull the rug out from under me
by telling Lockheed Martin that they wrote MFX --- they would explain to
Lockheed Martin that they are geniuses who deserve to get rich!
Everybody is a liar - which automatically leads to
HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
GO BACK TO YOUR CAGE AND BARK OR NOT.
Another made up piece of lies - just to make you feel good.
I did my job at MPE as consultant,LIAR LIAR LIAR - YOU ARE DOING WELL.
which triggered tmy FORTH BOOKSHELF on amazon https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
What have you contributed over the last 30 years
- except of often dayly rants and
accusations of probably everybody here.
To state that my letter to Testra and the kind answer from there was started without reason
is the biggest lie you ever told.
You have attacked me over the last 10 years for no real reason... and 1444 views here now
- it is all here on CLF so you can check
for no real reason.
So I wondered what Testra would say about you,
and it ended up in the probably most read post of CLF with about 4400 reads now.
https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
It will be 4444 soon -
You cannot get closer to fours.
Have a nice day,
and May The Fours Be With You.
On Sunday, April 30, 2023 at 4:26:49 AM UTC-4, Jurgen Pitaske wrote:
On Sunday, 30 April 2023 at 07:22:12 UTC+1, Jurgen Pitaske wrote:
On Sunday, 30 April 2023 at 07:14:16 UTC+1, Jurgen Pitaske wrote:
On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
Bullshit!No one from Testra ever attacked anyone on comp.lang.forthWhy did Testra attack me on comp.lang.forth with lies and insults?
or any other news group ever.
This entire thread was an unprovoked attack on me: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
Tom Hart was totally lying:
I let him go myself,
after I had given him a project to write a DXF converter to HPGL code.
He would not take any direction.
I scrapped the project.
I never even heard of HPGL before this attack. There was no HPGL project.
Also, I never got any direction in any of my work.
When I wrote the DXF to GCODE converter nobody told me about how Bezier Splines might work. I didn't know about Bezier Splines, and I assume
that the reason I wasn't told about Bezier Splines is that Tom and John Hart
don't know about them either. Tom Hart would just angrily tell me: "Just make a smooth line through all the tiny line segments!"
There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
weren't touching any other line segment and some touched other line segments.
I had no idea how to make a smooth line through this mess. I wished that I did
have some direction, but I never did. I wished that I had mind-reading ability
so that I could know what image the artist had intended with this mish-mash.
Tom Hart says that I'm too stupid to write a data-conversion program.
This isn't true. I was converting DXF code to GCODE within a couple of weeks
of starting the project. The problem was that the result was a mess. When I started the project I was told that this was a simple data-conversion
program, so I felt confident that I could finish in a few weeks. If I had been told
that I had to make a smooth line through a big mess of tiny line-segments,
I would have refused the job. If I had been told that I needed Bezier Splines
I would have refused the job because I don't know anything about the subject.
(This is where the comp.lang.forth trolls can spring into action and say that
they could easily implement Bezier Splines, so they get to be big internet experts
without writing any code, as usual).
Tom Hart was totally lying:
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long beforeThe original Forth Engine was a bit-slice processor.
we ever ran across Hugh.
This is unrelated to the MiniForth that was a VLIW processor.
Tom Hart is saying that MFX was written for the bit-slice processor and then
was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
All of that was written by John Perona who later wrote Multi-Edit. Even if there
had been some similarity between the original Forth Engine and the MiniForth,
I still wouldn't have looked at John Perona's code because I never look at other
people's code (that is like peering through a bedroom window to look at your
neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
who writes multi-page functions. He doesn't factor code at all.
Testra was originally called Hartronics and they advertised their "Forth Engine"
in Forth Dimensions, in case anybody cares (I don't).
It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
attacks on me over the last four years have been based on him obtaining 100%
support from Tom Hart.
It is very disingenuous for John Hart to now say:
No one from Testra ever attacked anyone on comp.lang.forthBullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
or any other news group ever.
Instead you provided Juergen Pintaske with 100% support for attacking me.
Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
Not referring to anyone specific, some people not only burn their bridgesIt was in the 1990s, less than five years after I left Testra, when I heard John Hart
they spend years taking the foundation down to bedrock with a jackhammer
until no evidence of what they accomplished remains.
(possibly Tom Hart doing an impersonation) say on speaker-phone that I had
accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
been saying this starting immediately after I left Testra but it was a few years later
when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
Tom Hart cares about loyalty! He expects employees to remain employed forever,
never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
Tom Hart has no sense of loyalty to his employees and will attack them in public.
Why didn't Testra just tell me when I left that leaving was an act of disloyaltyWHAT A MENTAL DESASTER AGAIN.
and that I would never get a reference? I made a fool out of myself by going to
job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
Most likely, Testra wanted me to go to these job interviews and describe MFX,
not for my benefit, but just as an advertisement for Testra's MiniForth processor.
They may have been hoping that Lockheed Martin would buy the MiniForth so
they could become wealthy, but they had no way to get Lockheed Martin's attention.
You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
"Hi! I've got a super-awesome processor! Would you like to buy it?" They may have believed (correctly) that for me to go to a job interview at
Lockheed Martin and describe MFX would be the only way that Lockheed Martin
would find out about the MiniForth --- but they would pull the rug out from under me
by telling Lockheed Martin that they wrote MFX --- they would explain to
Lockheed Martin that they are geniuses who deserve to get rich!
Everybody is a liar - which automatically leads to
HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
GO BACK TO YOUR CAGE AND BARK OR NOT.
Another made up piece of lies - just to make you feel good.
I did my job at MPE as consultant,LIAR LIAR LIAR - YOU ARE DOING WELL.
which triggered tmy FORTH BOOKSHELF on amazon https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
What have you contributed over the last 30 years
- except of often dayly rants and
accusations of probably everybody here.
To state that my letter to Testra and the kind answer from there was started without reason
is the biggest lie you ever told.
You have attacked me over the last 10 years for no real reason... and 1444 views here now
- it is all here on CLF so you can check
for no real reason.
So I wondered what Testra would say about you,
and it ended up in the probably most read post of CLF with about 4400 reads now.
https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
It will be 4444 soon -
You cannot get closer to fours.
Have a nice day,
and May The Fours Be With You.
This is without a doubt, the weirdest group I've ever seen.
--
Rick C.
-++- Get 1,000 miles of free Supercharging
-++- Tesla referral code - https://ts.la/richard11209
On Sunday, 30 April 2023 at 10:41:45 UTC+1, Lorem Ipsum wrote:
This is without a doubt, the weirdest group I've ever seen.
--
Rick C.
-++- Get 1,000 miles of free Supercharging
-++- Tesla referral code - https://ts.la/richard11209
And you are a much contributing member
On 30/04/2023 11:52 pm, Jurgen Pitaske wrote:you forgot to give us the link, but google helps https://www.biblegateway.com/verse/en/Revelation%2012%3A12
On Sunday, 30 April 2023 at 10:41:45 UTC+1, Lorem Ipsum wrote:
This is without a doubt, the weirdest group I've ever seen.
--
Rick C.
-++- Get 1,000 miles of free Supercharging
-++- Tesla referral code - https://ts.la/richard11209
And you are a much contributing memberLOL. The devil knows his own even when they don't.
A gifted programmer, with no experience was given a chance,
succeeded and was let go after he finished because there was
nothing for him to do.
...
Which indicated he was a creative individual and like many creative individuals, might be difficult to work with. A truth that's easily verified by reading posts on this and many other tech newsgroups.
On Mon, 31 Oct 2016 15:30:03 -0700 (PDT)
hughag...@nospicedham.gmail.com wrote:
How much cost is there in doing a JMP (unconditional)? This is always predicted correctly, so there shouldn't be much cost --- the¿Qué? Habla Inglés por favor. Lenguaje ensamblador no tiene una instrucción DROP. Los programadores del Forth en comp.lang.forth
trace-cache doesn't get emptied out and refilled --- OTOH, a new
16-byte paragraph has to be loaded and compiled because the jump destination is not likely to be in the same paragraph as the JMP is.
I wonder about this question because quite a lot of my primitives end
in DROP --- should I have a JMP to the DROP function, or should I
inline the DROP code? Also, is there any difference in speed between
a JMP with an 8-bit displacement and a JMP with a 16-bit displacement?
pueden saber sobre DROP. (Gracias, Google Translate.)
The x86 continues to be mysterious to me --- certainly the most complicated processor that I've ever worked with..."Do not pass Go. Do not collect $200."
hughag...@nospicedham.gmail.com wrote:
...
Rod Pemberton is a troll.Bye, Hugh.
Sincerely,
Frank
On Thursday, January 2, 2020 at 4:31:35 PM UTC-7, Rod Pemberton wrote:
Hugh called me racist for something that's not racist, but somethingI actually call Rod Pemberton a racist because he calls me a "minority." This is an example:
which actually pointed out racism. It pointed out racism against white people. The fact that you misinterpreted it and attempted to falsely
twist it into something it wasn't so that it fit into your biased political narrative, i.e., racism against black people, doesn't change
the fact that what I said was wholly non-racist and is still is true.
On Wednesday, January 1, 2020 at 7:56:17 PM UTC-7, hughag...@gmail.com wrote:
On Sunday, December 29, 2019 at 11:54:09 PM UTC-7, Rod Pemberton wrote:
For you, as a minority (in the U.S.), this would seem to be a rather bizarre and wholly illogical perspective. If the FBI is willing to discriminate against the majority race (white people, i.e., people of European descent) in the U.S., do you think that the FBI would even hesitate to not discriminate against minorities?
Piss off, racist troll!
I'm not actually a minority unless I explicitly play the minority card,
such as by applying for Affirmative Action. I have never done this.
Rod Pemberton cares if I am in a minority race or I am in
"the majority race (white people, i.e., people of European descent)."
That is racism.
That is also stupid because Spain is in Europe, so it is possible to
have an Hispanic name (Aguilar) and yet be white.
Even more stupid is that I may be of Spanish descent, but I'm a
5th generation American, so this is of historical interest at best.
In general, only racists care what my skin color is.
Weirdly, racist Mexicans say: "You can't speak Spanish. You're white!" Racist Whites say: "You have an Hispanic name. You're brown!"
So, my skin color depends upon the political agenda of the observer! lol
Rod Pemberton is also a stalker:
On Friday, March 7, 2014 at 3:23:53 PM UTC-7, Rod Pemberton wrote:
On Fri, 07 Mar 2014 02:48:18 -0500, <hughag...@yahoo.com> wrote:
On Wednesday, March 5, 2014 7:17:13 PM UTC-7, Albert van der Horst wrote:
I agree that Rod's response, especially the satellite photo of Brian's parents' house, was pretty creepy --- [..]
Satellite photos linked to addresses, phone numbers, and IPs are the modern phonebook and streetmap ... It's only creepy to those who
haven't moved into the modern era of Microsoft Streets and Trips,
Google's satellite maps, and, of course, "Big Brother." Or, it's
creepy for those who haven't accepted or willfully ignore the NSA
and CIA spying, and illegal U.S. government TSA body scans, etc.
You've been told about posting your IP too. Even so, you post from
your relative's IP. Why is that Hugh?
Originally, I intended to do that to you a while ago when you were being an ass and posting from your relatives house (Uncle?) in California. But, IIRC, you mentioned something about your relative being seriously ill.
So, I didn't think it would've been taken well by you, not that you would've
taken it well at any point in time ... But, hitting a guy when he's down, like when a relative has died or possibly dying, is completely tactless. But, I'm 100% sure that had I used that on *you* instead of the other guy, it would've resulted in a far more positive response from those present. Some here might've even openly applauded the effort as they've done for attacks on you in the past. So, just remember that you were the one who inspired such a response originally.
None of this is true.
I don't live in California, and I don't have an uncle, dying or otherwise. Rod Pemberton is a stalker. He tries to find people's home addresses
and then post satellite photos of the people's home on public forums
along with the home address. That is very creepy!
On Thursday, January 2, 2020 at 4:44:54 PM UTC-7, Rod Pemberton wrote:
On Wed, 1 Jan 2020 18:56:15 -0800 (PST)
hughag...@gmail.com wrote:
Piss off!
Didn't you say you got arrested for that?
Rod PembertonI've been telling Rod Pemberton for years: Piss off!
--
"It's OK to be White." <-- investigated by FBI as a hate crime
"Black Lives Matter." <-- not being investigated ...
I've never been arrested for doing so.
I intend to continue telling him this forever: Piss off!
I have only been banned from CLAX. This was here: https://groups.google.com/g/comp.lang.asm.x86/c/IVtSmnc2ddw/m/CH3O3IUjBAAJ
Usenet groups can be owned/moderated by an individual?
dxforth <dxforth@gmail.com> writes:
Usenet groups can be owned/moderated by an individual?
Moderated Usenet groups are moderated by individual moderators or
moderation teams.
On 2/05/2023 7:03 pm, Anton Ertl wrote:
dxforth <dxforth@gmail.com> writes:
Usenet groups can be owned/moderated by an individual?
Moderated Usenet groups are moderated by individual moderators or
moderation teams.
By what means?
The power of modern FPGA would blow people's minds, if they understood them. Advanced supercomputer have tens of thousands of chips with thousands of processes
running in each one with more computing power than a PC. The fear about AAI taking
over the world is based on the reality of what can be done with this power and how dangerous it would be if abused.
Restrictions won't reduce the danger, they'll make it more dangerous, more concentrated.
The solution to Big Tech having too much power is to empower people. Enable small business
to use robotics and automation to compete. Something like an open source platform programed
in Forth for automation would be the ideal tool to enable it. Focusing on solutions is the
only way out of the mess we're in, Attacks and flame wars are a DEAD END, they accomplish
NOTHING, and the din drowns out rational discourse.
On Friday, April 28, 2023 at 5:06:51 PM UTC-7, Lorem Ipsum wrote:
What mess??? I must have missed something.Not your fault if you still rely on MSM for your news.
Rick C.
America is in sharp decline on many fronts and MSM has been working overtime hiding it. The parts of our social economic system are strongly linked and
a series of errors by the current administration, as serious as the Titanic hittting an iceberg, have occured. The only solution is to get productivity growing faster than debt to prevent runaway inflation, and that's going
to require an autiomation revolution at the roots. The concentration of wealth by the Elite, not only stifles innovation it's extremely dangerous. After all, power corrupts and absolute power corrupts absolutely.
[Hugh] was a creative individual and like many creative
individuals, might be difficult to work with.
I have only been banned from CLAX.
On Friday, April 28, 2023 at 11:56:23 AM UTC-7, John Hart wrote:
The power of modern FPGA would blow people's minds, if they understood them.
Advanced supercomputer have tens of thousands of chips with thousands of processes
running in each one with more computing power than a PC. The fear about AAI taking
over the world is based on the reality of what can be done with this power and how dangerous it would be if abused.
Restrictions won't reduce the danger, they'll make it more dangerous, more concentrated.
The solution to Big Tech having too much power is to empower people. Enable small business
to use robotics and automation to compete. Something like an open source platform programed
in Forth for automation would be the ideal tool to enable it. Focusing on solutions is the
only way out of the mess we're in, Attacks and flame wars are a DEAD END, they accomplish
NOTHING, and the din drowns out rational discourse.
On Saturday, April 29, 2023 at 12:07:22 AM UTC-7, John Hart wrote:
On Friday, April 28, 2023 at 5:06:51 PM UTC-7, Lorem Ipsum wrote:
What mess??? I must have missed something.Not your fault if you still rely on MSM for your news.
Rick C.
America is in sharp decline on many fronts and MSM has been working overtime
hiding it. The parts of our social economic system are strongly linked and a series of errors by the current administration, as serious as the Titanic
hittting an iceberg, have occured. The only solution is to get productivity
growing faster than debt to prevent runaway inflation, and that's going
to require an autiomation revolution at the roots. The concentration of wealth by the Elite, not only stifles innovation it's extremely dangerous. After all, power corrupts and absolute power corrupts absolutely.
I remember that when I was writing MFX I was striving to succeed, so I
often worked late hours. John Hart worked late too. That's teamwork!
John Hart would often wander into my office carrying a 32-ounce cup
from Circle-K that was filled with what appeared to be lemonade.
He would deliver rambling monologues about weird off-topic subjects.
Here on comp.lang.forth he is lecturing Rick Collins on how AI could
take over the world, and how MSN is covering up the mess we are in.
John Hart is making a fool out of himself. For one thing, Rick Collins
is a nasty troll that I haven't responded to in many years, but John Hart
is treating him as a peer. This is just as dumb as treating Juergen Pintaske as a peer! Rick Collins and Juergen Pintaske are pigs! They aren't my peers. John Hart is mostly making a fool out of himself because he comes off as
a crackpot. I agree that the American economy is failing in pretty much the same way that the Soviet economy failed in 1991, but what am I supposed to do about it? Crackpot theories on internet forum aren't a positive contribution.
There were a wide variety of crackpot theories that John Hart would discourse
on, but he mostly was interested in the creationism and pro-life causes. When I visited Testra a few years ago, shortly after Testra's attack against me on
comp.lang.forth began, John Hart told me that he was retired and that his new "job"
was railing against abortion on internet forums (the railing was done on internet forums;
the abortions were presumably done at Planned Parenthood). Now abortion has been
made illegal in Arizona --- this is presumably why John Hart is back to his old job of
developing the RACE processor --- here he is with a vaporware announcement! On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
[Hugh] was a creative individual and like many creativeJohn Hart was very difficult to work with. Those rambling monologues could really weird out an employee! I thought of them as the "32-ounce discourses" because he would carry around his 32-ounce Circle-K cup while pontificating. I was suspicious that his drink was spiked, but I never bothered to get out of
individuals, might be difficult to work with.
my chair to smell his breath, so I don't know. A big part of my job was reeling
him in and getting him to just focus on the MiniForth development. I knew that
we would never succeed if we waste time worrying about AI taking over the world.
As for MSN, I don't care if it is better or worse than other free internet news. That
is like debating on whether it is worse to step in horse apples or cow patties.
Within the context of John Hart being the weirdest boss that I've ever had, I find it quite insulting that he is now all over the internet warning all potential
employers that they must not hire me because I'm difficult to work with.
I was willing to put up with him being difficult to work with because I understood that
creative people usually are --- but now he denounces me for being difficult to work with.
I succeeded at writing MFX! This was despite getting zero support from John Hart
in regard to advice on how to write MFX, and despite John Hart's weirdness. Instead of getting thanked, I get attacked for three decades running...
dxforth <dxforth@gmail.com> writes:
On 2/05/2023 7:03 pm, Anton Ertl wrote:
dxforth <dxforth@gmail.com> writes:
Usenet groups can be owned/moderated by an individual?
Moderated Usenet groups are moderated by individual moderators or
moderation teams.
By what means?
When you post to a moderated newsgroup, proper newsreaders send the
posting as email to the moderation address. If the moderator approves
the posting, the moderator adds an "Approved:" header and posts the
posting. Newsservers drop postings to moderated newsgroups that are
not approved.
On 2/05/2023 8:44 pm, Anton Ertl wrote:
dxforth <dxf...@gmail.com> writes:
On 2/05/2023 7:03 pm, Anton Ertl wrote:
dxforth <dxf...@gmail.com> writes:
Usenet groups can be owned/moderated by an individual?
Moderated Usenet groups are moderated by individual moderators or
moderation teams.
By what means?
When you post to a moderated newsgroup, proper newsreaders send the
posting as email to the moderation address. If the moderator approves
the posting, the moderator adds an "Approved:" header and posts the posting. Newsservers drop postings to moderated newsgroups that are
not approved.
Hopefully these groups come with a warning adults will be treated
as if they were children incapable of doing their own censoring.
Rated G.
On Tuesday, 2 May 2023 at 22:36:17 UTC+1, Hugh Aguilar wrote:<clip>
On Friday, April 28, 2023 at 11:56:23 AM UTC-7, John Hart wrote:
The power of modern FPGA would blow people's minds, if they understood them.
Advanced supercomputer have tens of thousands of chips with thousands of processes
running in each one with more computing power than a PC.
<big clip>flame wars are a DEAD END, they accomplish NOTHING,
and the din drowns out rational discourse.
On Tuesday, May 2, 2023 at 10:49:37 PM UTC-7, Jurgen Pitaske wrote:
On Tuesday, 2 May 2023 at 22:36:17 UTC+1, Hugh Aguilar wrote:<clip>
On Friday, April 28, 2023 at 11:56:23 AM UTC-7, John Hart wrote:
The power of modern FPGA would blow people's minds, if they understood them.
Advanced supercomputer have tens of thousands of chips with thousands of processes
running in each one with more computing power than a PC.
<big clip>flame wars are a DEAD END, they accomplish NOTHING,
and the din drowns out rational discourse.
The price of medium FPGAs has come down to the point dedicated processors are no longer
needed, Processor IP along with logic, easily fit for many applications. Our 16bit processor,
four motor control chanels, four high speed encoders, two PWM outputs, two SPI ports, an RS485
network interface and an RS232 port, fit in Lattice's 7000 LUT device with room to spare.
We've been working on the development system for 30 years. Started with a Karnaugh map
solver, (carmap) optomized for PLDs with a Forth program defining the function. When we switched
to FPGAs it became obvious a different approach was needed for both data and control.
The Forth community has always been interested in Forth processors. Forth, being extensible, is
the ideal language for an extensible processor. And the reason posting in this forum is to see if
there's any interest in an open source tool to design reconfigurable processors. If so I'll explain
the workings of the program.
On Tuesday, May 2, 2023 at 10:49:37 PM UTC-7, Jurgen Pitaske wrote:
On Tuesday, 2 May 2023 at 22:36:17 UTC+1, Hugh Aguilar wrote:<clip>
On Friday, April 28, 2023 at 11:56:23 AM UTC-7, John Hart wrote:
The power of modern FPGA would blow people's minds, if they understood them.
Advanced supercomputer have tens of thousands of chips with thousands of processes
running in each one with more computing power than a PC.
<big clip>flame wars are a DEAD END, they accomplish NOTHING,
and the din drowns out rational discourse.
The price of medium FPGAs has come down to the point dedicated processors are no longer
needed, Processor IP along with logic, easily fit for many applications. Our 16bit processor,
four motor control chanels, four high speed encoders, two PWM outputs, two SPI ports, an RS485
network interface and an RS232 port, fit in Lattice's 7000 LUT device with room to spare.
We've been working on the development system for 30 years. Started with a Karnaugh map
solver, (carmap) optomized for PLDs with a Forth program defining the function. When we switched
to FPGAs it became obvious a different approach was needed for both data and control.
The Forth community has always been interested in Forth processors. Forth, being extensible, is
the ideal language for an extensible processor. And the reason posting in this forum is to see if
there's any interest in an open source tool to design reconfigurable processors. If so I'll explain
the workings of the program.
jrh
Really looking forward to some more of your work.
And I have a Lattice 7k board here.
If I remember correctly and it has not changed, it is easy using just the Lattice Programmer -
just to get started and see the LEDs flash and the Servos turn.
One option would be to use dropbox to store the files,
and a link here when news have happened.
Github as well.
The Forth facebook group would be an option to distribute the information. https://www.facebook.com/groups/PROGRAMMINGFORTH
And the Minimalist group is very active https://www.facebook.com/groups/minimalistcomputing
On Saturday, May 6, 2023 at 12:09:32 AM UTC-7, Jurgen Pitaske wrote:
Really looking forward to some more of your work.We finally have a complete V file with all modules checked against the software simulation of a small set of 4th words.
And I have a Lattice 7k board here.
If I remember correctly and it has not changed, it is easy using just the Lattice Programmer -
just to get started and see the LEDs flash and the Servos turn.
One option would be to use dropbox to store the files,
and a link here when news have happened.
Github as well.
The Forth facebook group would be an option to distribute the information. https://www.facebook.com/groups/PROGRAMMINGFORTH
And the Minimalist group is very active https://www.facebook.com/groups/minimalistcomputing
Designing and getting Fpga4th to make the V file was more difficult than designing the 32bit 4th processor for our motion
control product. (16 cooridinated axis for our 7A 100V motor drivers, 2 cooridinated pwm outputs for lasers, printers etc,
a USB, SPI, rs485 and rs232 interface, 64Mb dram, 250Kb sram.)
It would be in our best interest for Fpga4th to become an open source project IF enough forth programers were interested
in continuing its development. Its based on an extension of Forth called 4thSets, which would also become
an open source project.
jrh
Reality is an information process, set in motion and sustained by God for a purpose.
Understanding the purpose is more important than knowing anything about anything.
boards are fabbed and delivered to the assembly house for stuffing. PCBWay forgot to make a stencil for the bottom side. I hope the assembly house can get one made locally (at greater cost) so I don't have to wait a week for PCBWay. Always something...=+
On Saturday, May 6, 2023 at 12:09:32 AM UTC-7, Jurgen Pitaske wrote:
Really looking forward to some more of your work.We finally have a complete V file with all modules checked against the software simulation of a small set of 4th words.
And I have a Lattice 7k board here.
If I remember correctly and it has not changed, it is easy using just the Lattice Programmer -
just to get started and see the LEDs flash and the Servos turn.
One option would be to use dropbox to store the files,
and a link here when news have happened.
Github as well.
The Forth facebook group would be an option to distribute the information. https://www.facebook.com/groups/PROGRAMMINGFORTH
And the Minimalist group is very active https://www.facebook.com/groups/minimalistcomputing
Designing and getting Fpga4th to make the V file was more difficult than designing the 32bit 4th processor for our motion
control product. (16 cooridinated axis for our 7A 100V motor drivers, 2 cooridinated pwm outputs for lasers, printers etc,
a USB, SPI, rs485 and rs232 interface, 64Mb dram, 250Kb sram.)
It would be in our best interest for Fpga4th to become an open source project IF enough forth programers were interested
in continuing its development. Its based on an extension of Forth called 4thSets, which would also become
an open source project.
jrh
Reality is an information process, set in motion and sustained by God for a purpose.
Understanding the purpose is more important than knowing anything about anything.
Is there any documentation available
- even just a smaller portion
- for people to have a look and switch an LED on? ...
Some of the people in the FIG Meeting might be very interested.
And it would be very interesting to know which FPGA Board could be used.
On Saturday, May 6, 2023 at 12:09:32 AM UTC-7, Jurgen Pitaske wrote:
Really looking forward to some more of your work.We finally have a complete V file...
It would be in our best interest for Fpga4th to become an open source project
IF enough forth programers were interested in continuing its development. Its based on an extension of Forth called 4thSets, which would also become an open source project.
Reality is an information process, set in motion and sustained by God for a purpose.
Understanding the purpose is more important than knowing anything about anything.
On Monday, 25 September 2023 at 00:44:58 UTC+1, Hugh Aguilar wrote:
On Friday, September 22, 2023 at 5:52:41 PM UTC-7, John Hart wrote:
On Saturday, May 6, 2023 at 12:09:32 AM UTC-7, Jurgen Pitaske wrote:
Really looking forward to some more of your work.We finally have a complete V file...
John Hart accepts Juergen Pintaske as his peer! LOL
That really says quite a lot about John Hart!
It would be in our best interest for Fpga4th to become an open source projectWhy is it in the best interests of Testra to make FPGA4TH and 4THSETS open-source? Is it because Testra's software is full of bugs and you hope that somebody will debug it for you?
IF enough forth programers were interested in continuing its development.
Its based on an extension of Forth called 4thSets, which would also become
an open source project.
You aren't any good at programming!You find it all here,
This is why you needed me to write MFX (assembler, simulator and
Forth cross-compiler for the MiniForth) --- you weren't capable of writing this
yourself, and your employeed Steve Brault wasn't capable either --- but you were
also ashamed of the fact that you needed to hire outside help, so you refused
to admit afterward that I had written MFX. The liar Tom Hart says: --------------------------------------------------------------
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long before we ever ran across Hugh.
--------------------------------------------------------------
Reality is an information process, set in motion and sustained by God for a purpose.John Hart is still pretending that he understands God's purpose! LOL
Understanding the purpose is more important than knowing anything about anything.
John Hart doesn't know anything about anything --- he is an arrogant clown.
all of the people that wanted to comment.
Please dump your shit elswhere.
On Friday, September 22, 2023 at 5:52:41 PM UTC-7, John Hart wrote:
On Saturday, May 6, 2023 at 12:09:32 AM UTC-7, Jurgen Pitaske wrote:
Really looking forward to some more of your work.We finally have a complete V file...
John Hart accepts Juergen Pintaske as his peer! LOL
That really says quite a lot about John Hart!
It would be in our best interest for Fpga4th to become an open source projectWhy is it in the best interests of Testra to make FPGA4TH and 4THSETS open-source? Is it because Testra's software is full of bugs and you hope that somebody will debug it for you?
IF enough forth programers were interested in continuing its development. Its based on an extension of Forth called 4thSets, which would also become an open source project.
You aren't any good at programming!
This is why you needed me to write MFX (assembler, simulator and
Forth cross-compiler for the MiniForth) --- you weren't capable of writing this
yourself, and your employeed Steve Brault wasn't capable either --- but you were
also ashamed of the fact that you needed to hire outside help, so you refused
to admit afterward that I had written MFX. The liar Tom Hart says: --------------------------------------------------------------
[Hugh] had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version was based upon our original Forth Engine done long before we ever ran across Hugh.
--------------------------------------------------------------
Reality is an information process, set in motion and sustained by God for a purpose.John Hart is still pretending that he understands God's purpose! LOL
Understanding the purpose is more important than knowing anything about anything.
John Hart doesn't know anything about anything --- he is an arrogant clown.
XBCS: This is likely a transformation or a command to convert the previous value.
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