Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit. One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher
voltage than the source or drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the source or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and I'm
not interested enough to try and work how it is actually working.
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the source or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and I'm
not interested enough to try and work how it is actually working.
--
Bill Sloman, sydney
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the source or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and I'm
not interested enough to try and work how it is actually working.
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post. >> I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and I'm
not interested enough to try and work how it is actually working.
I've modified the circuit to make sure that FET gate doesn't get forward-biased.
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.
Bill Sloman, Sydney
Version 4
SHEET 1 3828 932
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FLAG 208 -80 gate
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SYMBOL njf 192 64 M90
WINDOW 0 -37 23 VRight 2
WINDOW 3 -9 -3 VRight 2
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SYMBOL voltage -384 416 R0
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SYMATTR Type diode
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SYMATTR Type diode
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WINDOW 0 0 56 VBottom 2
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SYMBOL OpAmps\\LT1058 1536 592 R0
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SYMBOL res 1632 640 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R33
SYMATTR Value 820k
SYMBOL cap 1312 736 M0
SYMATTR InstName C15
SYMATTR Value 1000n
SYMBOL cap 1776 768 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C17
SYMATTR Value 1000n
SYMBOL res 1360 496 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R35
SYMATTR Value 10k
SYMBOL cap 2032 -288 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C18
SYMATTR Value 100n
SYMBOL schottky 2272 -208 R180
WINDOW 3 24 0 Left 2
WINDOW 0 24 64 Left 2
SYMATTR Value BAS40HY
SYMATTR InstName D4
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 2272 -288 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R38
SYMATTR Value 100k
SYMBOL res 2064 -384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R39
SYMATTR Value 100k
SYMBOL schottky 1952 528 M0
SYMATTR Value BAS40HY
SYMATTR InstName D10
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 1920 704 R0
SYMATTR InstName R41
SYMATTR Value 820k
SYMBOL res 2336 464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R42
SYMATTR Value 100k
SYMBOL OpAmps\\LT1058 2128 592 R0
SYMATTR InstName U10
SYMBOL res 2224 640 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R43
SYMATTR Value 820k
SYMBOL cap 1904 736 M0
SYMATTR InstName C21
SYMATTR Value 1000n
SYMBOL cap 2368 768 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C23
SYMATTR Value 1000n
SYMBOL res 1952 496 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R45
SYMATTR Value 10k
SYMBOL res 1872 -128 M0
SYMATTR InstName R46
SYMATTR Value 1.5k
SYMBOL OpAmps\\LT1058 1408 -192 R0
SYMATTR InstName U7
SYMBOL OpAmps\\LT1058 2000 -192 R0
SYMATTR InstName U9
SYMBOL cap 912 528 R90
WINDOW 0 8 66 VBottom 2
WINDOW 3 -18 -26 VTop 2
SYMATTR InstName C11
SYMATTR Value 10000n
SYMATTR SpiceLine V=25 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM188R61E106MA73" type="X5R"
SYMBOL cap 1504 528 R90
WINDOW 0 6 70 VBottom 2
WINDOW 3 -22 -25 VTop 2
SYMATTR InstName C13
SYMATTR Value 10000n
SYMATTR SpiceLine V=25 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM188R61E106MA73" type="X5R"
SYMBOL cap 2096 528 R90
WINDOW 0 8 70 VBottom 2
WINDOW 3 -19 -25 VTop 2
SYMATTR InstName C14
SYMATTR Value 10000n
SYMATTR SpiceLine V=25 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM188R61E106MA73" type="X5R"
SYMBOL cap -320 512 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C16
SYMATTR Value 10000n
SYMATTR SpiceLine V=25 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM188R61E106MA73" type="X5R"
SYMBOL res 704 384 R0
SYMATTR InstName R28
SYMATTR Value 560k
SYMBOL res 256 528 R180
WINDOW 0 40 70 Left 2
WINDOW 3 45 42 Left 2
SYMATTR InstName R30
SYMATTR Value 200k
SYMBOL res 480 -688 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 6800k
TEXT -408 -744 Left 2 !.tran 0 20 0 1u uic
TEXT -416 -816 Left 2 !.options plotwinsize=0 numdgt=7 method=trap
TEXT -424 -648 Left 2 ;1kHz low distortion sinewave oscillator.
TEXT -424 -616 Left 2 ;Approaching 130dB. Edward Rawde 30 Jan 2025.
TEXT 1352 -640 Left 2 ;As modifed by Bill Sloman 1 Feb 2025, greatly degrading the distortion performance, but fixing some
start-up problems.
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else. >>>>>
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post. >>> I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and I'm
not interested enough to try and work how it is actually working.
I've modified the circuit to make sure that FET gate doesn't get forward-biased.
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
Did he say why?
I've swapped in a J111. The integrator around U6
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Sorry bill but I don't get why you would sabotage the circuit like that.
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at all.
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else. >>>>>>
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the
source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and
I'm
not interested enough to try and work how it is actually working.
I've modified the circuit to make sure that FET gate doesn't get forward-biased.
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
Did he say why?
I've swapped in a J111. The integrator around U6
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot
of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Sorry bill but I don't get why you would sabotage the circuit like that.
You aren't a quick study.
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at all.
Perhaps if you measure the distortion only when the stabilisation circuit isn't feeding anything into the integrator wrapped
around U6.
The current feed to set the output level by balancing out the inputs from the rectifiers was feeding in current when it should
have been sucking it out, so it wasn't a well thought-out design.
Here's a version of that circuit which does work sensibly, even if the harmonic content of the output is only about 60DB below
the fundamental.
I you're using polyphase sampling you may as well use a svo. The
LT115 is not a good choice - it's phase margin is close to zero and it
is liable to sing at about 25MHz.
On 2/02/2025 4:26 am, Edward Rawde wrote:...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?
I'll pass.
--
Bill Sloman, Sydney
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else. >>>>>>>
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the
source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and
I'm
not interested enough to try and work how it is actually working.
I've modified the circuit to make sure that FET gate doesn't get forward-biased.
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
Did he say why?
I've swapped in a J111. The integrator around U6
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot
of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Sorry bill but I don't get why you would sabotage the circuit like that.
You aren't a quick study.
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at all.
Perhaps if you measure the distortion only when the stabilisation circuit isn't feeding anything into the integrator wrapped
around U6.
The current feed to set the output level by balancing out the inputs from the rectifiers was feeding in current when it should
have been sucking it out, so it wasn't a well thought-out design.
Here's a version of that circuit which does work sensibly, even if the harmonic content of the output is only about 60DB below
the fundamental.
But that's completely nuts Bill.
If I really do want 1kHz with -133dB harmonic distortion in reality then I'm prepared to wait 20 seconds for it.
In fact I'm prepared to wait a minute or two if that's what it takes for the harmonic distortion to go down to -133dB.
If there's a problem with the design around U6 then why doesn't that also apply to U7 and U9?
It's not intended as a volume production design. I might make two or three boards and test it.
But I don't have equipment capable of measuring -133dB harmonic distortion.
I would also be prepared to make adjustments to the circuit for minimum distortion.
This circuit might have up to six adjustments if built for real so it can be adjusted for correct output level and minimum
distortion.
The circuit included below might be my final offering on this matter.
There's nothing visible at 2kHz and 3kHz is barely visible.
It requires only a cheap quad op amp package in addition to the two LT1115 devices.
If you can show me a circuit which has -133dB harmonic distortion and also faster settling time then I'd like to see it but if
you're going to insist that it has to have only -60 dB harmonic distortion performance (which interestingly is about that of your
own circuit) just because the settling time can be made shorter then I'm sorry but all that's going to do is make me wonder about
your mental health.
If you believe that a real version of the circuit below could not be adjusted to better than -130dB (with suitable test equipment)
then please let me know.
It might take an hour to complete the adjustments but that's ok with me because as previously stated it's not intended as a
production design which just works after assembly.
It takes my computer about 10 minutes (LTSpice 24.1.1) to complete 20 seconds of simulation for the following circuit.
I usually watch the output and the current in each of the four diodes.
When it's done, take a sample of the output near 20s and FFT with Blackman-Harris window.
On 2/02/2025 3:05 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnmpgh$dafg$1@dont-email.me...
On 2/02/2025 4:26 am, Edward Rawde wrote:...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?
I'll pass.
If your circuit design skills are demonstrated by a circuit which uses 93 components (which includes 9 transistors and 10
integrated
circuits) and only gets 60dB down on harmonics then I agree that pass is for the best.
If you think that circuit design skills can be assessed by counting components, we can draw our own conclusions.
--
Bill Sloman, Sydney
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnmpgh$dafg$1@dont-email.me...
On 2/02/2025 4:26 am, Edward Rawde wrote:...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?
I'll pass.
If your circuit design skills are demonstrated by a circuit which uses 93 components (which includes 9 transistors and 10 integrated
circuits) and only gets 60dB down on harmonics then I agree that pass is for the best.
"JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:0rgtpjlopt521i824vurfan2jkiljk5ph3@4ax.com...
I you're using polyphase sampling you may as well use a svo. The
LT115 is not a good choice - it's phase margin is close to zero and it
is liable to sing at about 25MHz.
Very interesting circuit. Thank you.
Is there a suitable available alternative to LT1115?
I have seen LT1115 oscillate at 24 MHz in LTSpice 24.1.1
It doesn't seem to always happen and when it does a little extra load on the output seems to get rid of it.
2N4391 doesn't seem to be available at a reasonable price but J113 is.
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnn0gk$i856$1@dont-email.me...
On 2/02/2025 3:05 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnmpgh$dafg$1@dont-email.me...
On 2/02/2025 4:26 am, Edward Rawde wrote:...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?
I'll pass.
If your circuit design skills are demonstrated by a circuit which uses 93 components (which includes 9 transistors and 10
integrated circuits) and only gets 60dB down on harmonics then I agree that pass is for the best.
If you think that circuit design skills can be assessed by counting components, we can draw our own conclusions.
Stop making me laugh please Bill.
Who is "we" anyway. You sound like you speak for everyone here.
On Sat, 1 Feb 2025 12:26:28 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...You aren't a quick study.
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else. >>>>>>>>
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the
source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and
I'm
not interested enough to try and work how it is actually working.
I've modified the circuit to make sure that FET gate doesn't get forward-biased.
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
Did he say why?
I've swapped in a J111. The integrator around U6
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot
of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Sorry bill but I don't get why you would sabotage the circuit like that. >>>
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at all.
Perhaps if you measure the distortion only when the stabilisation circuit isn't feeding anything into the integrator wrapped
around U6.
The current feed to set the output level by balancing out the inputs from the rectifiers was feeding in current when it should
have been sucking it out, so it wasn't a well thought-out design.
Here's a version of that circuit which does work sensibly, even if the harmonic content of the output is only about 60DB below
the fundamental.
But that's completely nuts Bill.
If I really do want 1kHz with -133dB harmonic distortion in reality then I'm prepared to wait 20 seconds for it.
In fact I'm prepared to wait a minute or two if that's what it takes for the harmonic distortion to go down to -133dB.
If there's a problem with the design around U6 then why doesn't that also apply to U7 and U9?
It's not intended as a volume production design. I might make two or three boards and test it.
But I don't have equipment capable of measuring -133dB harmonic distortion. >>
I would also be prepared to make adjustments to the circuit for minimum distortion.
This circuit might have up to six adjustments if built for real so it can be adjusted for correct output level and minimum
distortion.
The circuit included below might be my final offering on this matter. >>There's nothing visible at 2kHz and 3kHz is barely visible.
It requires only a cheap quad op amp package in addition to the two LT1115 devices.
If you can show me a circuit which has -133dB harmonic distortion and also faster settling time then I'd like to see it but if
you're going to insist that it has to have only -60 dB harmonic distortion performance (which interestingly is about that of your
own circuit) just because the settling time can be made shorter then I'm sorry but all that's going to do is make me wonder about
your mental health.
If you believe that a real version of the circuit below could not be adjusted to better than -130dB (with suitable test equipment)
then please let me know.
It might take an hour to complete the adjustments but that's ok with me because as previously stated it's not intended as a
production design which just works after assembly.
It takes my computer about 10 minutes (LTSpice 24.1.1) to complete 20 seconds of simulation for the following circuit.
I usually watch the output and the current in each of the four diodes.
When it's done, take a sample of the output near 20s and FFT with Blackman-Harris window.
Version 4.1
SHEET 1 3828 932
WIRE 832 -768 832 -800
WIRE 336 -672 256 -672
WIRE 480 -672 400 -672
WIRE 832 -656 832 -688
WIRE 832 -656 720 -656
WIRE 832 -624 832 -656
WIRE 944 -624 832 -624
WIRE 720 -608 720 -656
WIRE 832 -608 832 -624
WIRE 944 -592 944 -624
WIRE 256 -576 256 -672
WIRE 336 -576 256 -576
WIRE 480 -576 480 -672
WIRE 480 -576 416 -576
WIRE 832 -496 832 -528
WIRE 944 -496 944 -528
WIRE -192 -480 -192 -512
WIRE 384 -464 384 -480
WIRE 480 -448 480 -576
WIRE 480 -448 416 -448
WIRE 576 -448 480 -448
WIRE 640 -448 576 -448
WIRE 720 -448 720 -528
WIRE 720 -448 640 -448
WIRE 1056 -448 720 -448
WIRE 1168 -448 1056 -448
WIRE 1296 -448 1168 -448
WIRE 1872 -448 1296 -448
WIRE 256 -432 256 -576
WIRE 352 -432 256 -432
WIRE 448 -416 416 -416
WIRE 464 -416 448 -416
WIRE 576 -400 576 -448
WIRE 1056 -400 1056 -448
WIRE 1168 -400 1168 -448
WIRE 1872 -400 1872 -448
WIRE -416 -384 -416 -480
WIRE -336 -368 -336 -400
WIRE 384 -368 384 -400
WIRE 1296 -368 1296 -448
WIRE 1328 -368 1296 -368
WIRE 1424 -368 1408 -368
WIRE 1520 -368 1504 -368
WIRE 16 -352 -144 -352
WIRE 1056 -304 1056 -320
WIRE 1168 -304 1168 -320
WIRE 1168 -304 1056 -304
WIRE 576 -288 576 -320
WIRE 1168 -288 1168 -304
WIRE 1520 -288 1520 -368
WIRE 1872 -288 1872 -320
WIRE -336 -272 -336 -304
WIRE -80 -272 -80 -304
WIRE -144 -256 -144 -352
WIRE -112 -256 -144 -256
WIRE 16 -240 16 -352
WIRE 16 -240 -48 -240
WIRE 48 -240 16 -240
WIRE 64 -240 48 -240
WIRE 256 -240 256 -432
WIRE -192 -224 -192 -400
WIRE -112 -224 -192 -224
WIRE -416 -208 -416 -304
WIRE 976 -192 880 -192
WIRE 1168 -192 1168 -224
WIRE 1168 -192 1040 -192
WIRE 1376 -192 1328 -192
WIRE 1520 -192 1520 -224
WIRE 1520 -192 1456 -192
WIRE 1728 -192 1680 -192
WIRE 1872 -192 1872 -224
WIRE 1872 -192 1808 -192
WIRE -192 -176 -192 -224
WIRE -192 -176 -256 -176
WIRE -80 -176 -80 -208
WIRE -192 -144 -192 -176
WIRE -256 -128 -256 -176
WIRE 448 -96 384 -96
WIRE 576 -96 576 -224
WIRE 576 -96 512 -96
WIRE 880 -96 880 -192
WIRE 976 -96 880 -96
WIRE 1168 -96 1168 -192
WIRE 1168 -96 1056 -96
WIRE 1328 -96 1328 -192
WIRE 1376 -96 1328 -96
WIRE 1520 -96 1520 -192
WIRE 1520 -96 1440 -96
WIRE 1680 -96 1680 -192
WIRE 1728 -96 1680 -96
WIRE 1872 -96 1872 -192
WIRE 1872 -96 1792 -96
WIRE 208 -80 160 -80
WIRE 256 -80 256 -160
WIRE 256 -80 208 -80
WIRE -256 -32 -256 -64
WIRE -192 -32 -192 -64
WIRE 160 -32 160 -80
WIRE 384 0 384 -96
WIRE 448 0 384 0
WIRE 576 0 576 -96
WIRE 576 0 528 0
WIRE 880 0 880 -96
WIRE 928 0 880 0
WIRE 1040 0 1008 0
WIRE 1168 0 1168 -96
WIRE 1168 0 1120 0
WIRE 1408 16 1408 0
WIRE 1760 16 1760 0
WIRE 1328 32 1328 -96
WIRE 1328 32 1264 32
WIRE 1376 32 1328 32
WIRE 1680 32 1680 -96
WIRE 1680 32 1616 32
WIRE 1728 32 1680 32
WIRE 1264 48 1264 32
WIRE 1520 48 1520 -96
WIRE 1520 48 1440 48
WIRE 1616 48 1616 32
WIRE 1872 48 1872 -96
WIRE 1872 48 1792 48
WIRE 256 64 256 -80
WIRE 1344 64 1328 64
WIRE 1376 64 1344 64
WIRE 1696 64 1680 64
WIRE 1728 64 1696 64
WIRE 464 96 464 80
WIRE 128 112 112 112
WIRE 160 112 160 48
WIRE 160 112 128 112
WIRE 192 112 160 112
WIRE 304 112 288 112
WIRE 336 112 304 112
WIRE 384 112 384 0
WIRE 384 112 336 112
WIRE 432 112 384 112
WIRE 960 112 960 96
WIRE 1408 112 1408 80
WIRE 1760 112 1760 80
WIRE 576 128 576 0
WIRE 576 128 496 128
WIRE 640 128 576 128
WIRE 672 128 640 128
WIRE 752 128 736 128
WIRE 880 128 880 0
WIRE 880 128 832 128
WIRE 928 128 880 128
WIRE 400 144 384 144
WIRE 432 144 400 144
WIRE 1168 144 1168 0
WIRE 1168 144 992 144
WIRE 896 160 880 160
WIRE 928 160 896 160
WIRE 1264 160 1264 128
WIRE 1616 160 1616 128
WIRE 112 192 112 112
WIRE 192 192 112 192
WIRE 336 192 336 112
WIRE 336 192 272 192
WIRE 464 192 464 160
WIRE 960 208 960 176
WIRE 640 256 640 128
WIRE 1264 256 1264 224
WIRE 1264 256 640 256
WIRE 112 320 112 192
WIRE 192 320 112 320
WIRE 336 320 272 320
WIRE 1168 320 1168 144
WIRE 1168 320 416 320
WIRE 1616 320 1616 224
WIRE 1616 320 1168 320
WIRE 1712 320 1616 320
WIRE 1840 320 1792 320
WIRE 2000 320 1904 320
WIRE 2064 320 2000 320
WIRE 2064 384 2064 320
WIRE 2064 480 2064 464
FLAG 384 -480 V+
FLAG 464 80 V+
FLAG 960 96 V+
FLAG 208 -80 gate
FLAG 128 112 drn
FLAG 2064 480 0
FLAG 2000 320 output
FLAG -416 -208 0
FLAG 384 -368 0
FLAG 464 192 0
FLAG 960 208 0
FLAG -416 -480 V+
FLAG 448 -416 half
FLAG 400 144 half
FLAG -80 -176 0
FLAG -80 -304 V+
FLAG 48 -240 half
FLAG -192 -32 0
FLAG -192 -512 V+
FLAG -256 -32 0
FLAG 304 112 src
FLAG 832 -496 0
FLAG 832 -800 V+
FLAG 944 -496 0
FLAG 1408 0 V+
FLAG 1408 112 0
FLAG 1760 0 V+
FLAG 1760 112 0
FLAG -336 -272 0
FLAG -336 -400 V+
FLAG 640 -448 levelfb
FLAG 896 160 half
FLAG 1344 64 half
FLAG 1696 64 half
SYMBOL njf 192 64 M90
WINDOW 0 -37 23 VRight 2
WINDOW 3 -9 -3 VRight 2
SYMATTR InstName J1
SYMATTR Value J113
SYMBOL voltage -416 -400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 10 135 Left 2
WINDOW 0 10 0 Left 2
WINDOW 3 15 104 Left 2
SYMATTR InstName V2
SYMATTR Value 36
SYMBOL schottky 1152 -224 M180
WINDOW 3 24 0 Left 2
WINDOW 0 24 64 Left 2
SYMATTR Value BAS40HY
SYMATTR InstName D2
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 176 176 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 22
SYMBOL res 176 -48 M0
WINDOW 0 38 42 Left 2
WINDOW 3 36 66 Left 2
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL res 272 -144 R180
WINDOW 0 40 70 Left 2
WINDOW 3 45 42 Left 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 320 -560 R270
WINDOW 0 33 55 VTop 2
WINDOW 3 -3 55 VBottom 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL res 1184 -304 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R6
SYMATTR Value 470k
SYMBOL cap 400 -688 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 10000n
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM185R60J106ME15" type="X5R"
SYMBOL res 1072 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 15k
SYMBOL res 848 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 8.2K
SYMBOL cap 1040 -208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMATTR SpiceLine V=16 Irms=647m Rser=0.0322889 Lser=0 mfg="KEMET" pn="C0201C103K4PAC" type="X5R"
SYMBOL cap 736 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 22n
SYMATTR SpiceLine V=4 Irms=356m Rser=0.150334 Lser=0 mfg="KEMET" pn="C0402C223K7PAC" type="X5R"
SYMBOL res 544 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R13
SYMATTR Value 10k
SYMBOL cap 512 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 22p
SYMATTR SpiceLine V=16 Irms=0 Rser=0.3482 Lser=551p mfg="Würth Elektronik" pn="885012006019 WCAP-CSGP 0603" type="NP0"
SYMBOL res 432 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 1371
SYMBOL res 704 -624 R0
SYMATTR InstName R17
SYMATTR Value 430k
SYMBOL res 1808 304 R90
WINDOW 0 -4 57 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 600
SYMBOL res 2080 480 R180
WINDOW 0 47 75 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R8
SYMATTR Value 600
SYMBOL res -208 -384 M180
WINDOW 0 40 70 Left 2
WINDOW 3 37 41 Left 2
SYMATTR InstName R5
SYMATTR Value 100k
SYMBOL res -208 -48 M180
WINDOW 0 40 70 Left 2
WINDOW 3 38 43 Left 2
SYMATTR InstName R10
SYMATTR Value 100k
SYMBOL cap -240 -64 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMATTR SpiceLine V=50 Irms=291m Rser=0.34258 Lser=0 mfg="KEMET" pn="C0805F103K5RAC" type="X7R"
SYMBOL cap 1904 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 10000n
SYMATTR SpiceLine V=25 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM188R61E106MA73" type="X5R"
SYMBOL res 1024 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 150k
SYMBOL res 288 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R15
SYMATTR Value 8.2k
SYMBOL res 1136 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R16
SYMATTR Value 47k
SYMBOL OpAmps\\LT1058 -80 -304 R0
SYMATTR InstName U5
SYMBOL OpAmps\\LT1058 384 -496 M0
SYMATTR InstName U6
SYMBOL res 816 -784 R0
SYMATTR InstName R19
SYMATTR Value 91k
SYMBOL res 816 -624 R0
SYMATTR InstName R20
SYMATTR Value 120k
SYMBOL cap 928 -528 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C7
SYMATTR Value 10n
SYMATTR SpiceLine V=50 Irms=291m Rser=0.34258 Lser=0 mfg="KEMET" pn="C0805F103K5RAC" type="X7R"
SYMBOL OpAmps\\LT1115 464 64 R0
SYMATTR InstName U4
SYMBOL OpAmps\\LT1115 960 80 R0
SYMATTR InstName U3
SYMBOL schottky 560 -224 M180
WINDOW 3 24 0 Left 2
WINDOW 0 24 64 Left 2
SYMATTR Value BAS40HY
SYMATTR InstName D1
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 592 -304 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R18
SYMATTR Value 470k
SYMBOL res 1280 32 M0
SYMATTR InstName R27
SYMATTR Value 1.5k
SYMBOL cap 1440 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C12
SYMATTR Value 100n
SYMBOL schottky 1504 -224 M180
WINDOW 3 24 0 Left 2
WINDOW 0 24 64 Left 2
SYMATTR Value BAS40HY
SYMATTR InstName D3
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 1408 -352 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R36
SYMATTR Value 470k
SYMBOL res 1472 -208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R29
SYMATTR Value 100k
SYMBOL cap 1792 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C18
SYMATTR Value 100n
SYMBOL schottky 1856 -224 M180
WINDOW 3 24 0 Left 2
WINDOW 0 24 64 Left 2
SYMATTR Value BAS40HY
SYMATTR InstName D4
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 1888 -304 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R38
SYMATTR Value 470k
SYMBOL res 1824 -208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R39
SYMATTR Value 100k
SYMBOL res 1632 32 M0
SYMATTR InstName R46
SYMATTR Value 1.5k
SYMBOL OpAmps\\LT1058 1408 -16 R0
SYMATTR InstName U7
SYMBOL OpAmps\\LT1058 1760 -16 R0
SYMATTR InstName U9
SYMBOL cap -352 -304 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C16
SYMATTR Value 10000n
SYMATTR SpiceLine V=25 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM188R61E106MA73" type="X5R"
SYMBOL cap 1248 224 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C8
SYMATTR Value 10000n
SYMATTR SpiceLine V=25 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM188R61E106MA73" type="X5R"
SYMBOL res 1424 -384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R22
SYMATTR Value 20k
SYMBOL res 1072 -416 M0
SYMATTR InstName R21
SYMATTR Value 7.5Meg
SYMBOL cap 1600 224 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C9
SYMATTR Value 10000n
SYMATTR SpiceLine V=25 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM188R61E106MA73" type="X5R"
TEXT -496 136 Left 2 !.tran 0 20 1m 1u uic
TEXT -496 88 Left 2 !.options plotwinsize=0 numdgt=7 method=trap
TEXT -424 -648 Left 2 ;1kHz low distortion sinewave oscillator.
TEXT -424 -616 Left 2 ;133dB. Edward Rawde 31 Jan 2025.
I you're using polyphase sampling you may as well use a svo. The
LT115 is not a good choice - it's phase margin is close to zero and it
is liable to sing at about 25MHz.
Version 4
SHEET 1 3020 1316
WIRE 432 -160 64 -160
WIRE 1152 -160 512 -160
WIRE 64 -48 64 -160
WIRE 432 -48 64 -48
WIRE 752 -48 512 -48
WIRE 64 32 64 -48
WIRE 176 32 64 32
WIRE 320 32 256 32
WIRE 608 32 560 32
WIRE 752 32 752 -48
WIRE 752 32 672 32
WIRE 1008 32 960 32
WIRE 1152 32 1152 -160
WIRE 1152 32 1072 32
WIRE 64 144 64 32
WIRE 176 144 64 144
WIRE 320 144 320 32
WIRE 432 144 320 144
WIRE 560 144 560 32
WIRE 560 144 512 144
WIRE 608 144 560 144
WIRE 752 144 752 32
WIRE 832 144 752 144
WIRE 960 144 960 32
WIRE 960 144 912 144
WIRE 1008 144 960 144
WIRE 320 160 320 144
WIRE 320 160 240 160
WIRE 752 160 752 144
WIRE 752 160 672 160
WIRE 1152 160 1152 32
WIRE 1152 160 1072 160
WIRE 1184 160 1152 160
WIRE 176 176 64 176
WIRE 608 176 576 176
WIRE 1008 176 976 176
WIRE 576 208 576 176
WIRE 976 208 976 176
WIRE 64 288 64 176
WIRE 160 288 64 288
WIRE 560 288 240 288
WIRE 752 288 752 160
WIRE 752 288 560 288
WIRE 752 336 752 288
WIRE -224 400 -224 384
WIRE -224 400 -288 400
WIRE -288 416 -288 400
WIRE -224 416 -224 400
WIRE 64 432 64 288
WIRE 752 448 752 416
WIRE 864 448 752 448
WIRE 720 464 688 464
WIRE 720 496 720 464
WIRE 752 496 752 448
WIRE 864 496 864 448
WIRE 736 608 736 560
WIRE 864 608 864 576
WIRE 864 608 736 608
WIRE 320 656 320 160
WIRE 560 656 560 288
WIRE 736 656 736 608
WIRE 1152 656 1152 160
WIRE 64 688 64 512
WIRE -320 752 -400 752
WIRE -176 752 -256 752
WIRE 320 752 320 720
WIRE 560 752 560 720
WIRE 736 752 736 720
WIRE 1152 752 1152 720
WIRE -400 848 -400 752
WIRE -320 848 -400 848
WIRE -176 848 -176 752
WIRE -176 848 -256 848
WIRE 320 880 320 832
WIRE 560 880 560 832
WIRE 560 880 320 880
WIRE 736 880 736 832
WIRE 736 880 560 880
WIRE 1152 880 1152 832
WIRE 1152 880 736 880
WIRE 64 912 64 768
WIRE 64 912 -16 912
WIRE -400 928 -400 848
WIRE -384 928 -400 928
WIRE -288 928 -304 928
WIRE -176 928 -176 848
WIRE -176 928 -224 928
WIRE -16 944 -16 912
WIRE 320 976 320 880
WIRE 64 992 64 912
WIRE -176 1008 -176 928
WIRE -400 1040 -400 928
WIRE -320 1040 -400 1040
WIRE -176 1056 -176 1008
WIRE -176 1056 -256 1056
WIRE -144 1056 -176 1056
WIRE -16 1056 -16 1024
WIRE -16 1056 -64 1056
WIRE 16 1056 -16 1056
WIRE -320 1072 -352 1072
WIRE -352 1120 -352 1072
WIRE -400 1184 -400 1040
WIRE 320 1184 320 1056
WIRE 320 1184 -400 1184
WIRE 400 1184 320 1184
WIRE 528 1184 480 1184
FLAG 576 208 0
FLAG 976 208 0
FLAG -288 416 0
FLAG -224 304 vcc
FLAG -224 496 vee
FLAG 1184 160 vout
FLAG 64 1088 0
FLAG -288 1024 vcc
FLAG -288 1088 vee
FLAG -352 1120 0
FLAG 688 464 0
FLAG 592 1184 vee
FLAG -176 1008 vx
SYMBOL res 272 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 528 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 16K
SYMBOL res 928 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 16K
SYMBOL cap 672 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL cap 1072 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res 528 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 528 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 82k
SYMBOL res 256 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 10K
SYMBOL res 48 416 R0
SYMATTR InstName R7
SYMATTR Value 470
SYMBOL voltage -224 288 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -224 400 R0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL njf 16 992 R0
SYMATTR InstName J1
SYMATTR Value 2N4391
SYMBOL res -160 1040 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 100k
SYMBOL res 0 1040 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R9
SYMATTR Value 100k
SYMBOL cap -320 832 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1u
SYMBOL res 384 1200 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R10
SYMATTR Value 330K
SYMBOL diode 528 1200 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL res 304 960 R0
SYMATTR InstName R11
SYMATTR Value 47K
SYMBOL OpAmps\\LT1679 -288 1056 R0
SYMATTR InstName U7
SYMBOL cap -288 912 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 10U
SYMBOL res -400 912 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 10K
SYMBOL diode -256 768 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D3
SYMATTR Value 1N914
SYMBOL res 880 592 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R18
SYMATTR Value 10K
SYMBOL res 768 432 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R19
SYMATTR Value 10k
SYMBOL diode 336 656 M0
SYMATTR InstName D2
SYMATTR Value 1N914
SYMBOL diode 576 656 M0
SYMATTR InstName D12
SYMATTR Value 1N914
SYMBOL diode 720 656 R0
SYMATTR InstName D13
SYMATTR Value 1N914
SYMBOL diode 1168 656 M0
SYMATTR InstName D14
SYMATTR Value 1N914
SYMBOL res 80 672 M0
SYMATTR InstName R29
SYMATTR Value 95
SYMBOL OpAmps\\opamp 208 96 R0
SYMATTR InstName U5
SYMATTR SpiceLine Aol=5Meg
SYMATTR SpiceLine2 GBW=60Meg
SYMBOL OpAmps\\opamp 640 96 R0
SYMATTR InstName U6
SYMATTR SpiceLine Aol=5Meg
SYMATTR SpiceLine2 GBW=60Meg
SYMBOL OpAmps\\opamp 1040 96 R0
SYMATTR InstName U8
SYMATTR SpiceLine Aol=5Meg
SYMATTR SpiceLine2 GBW=60Meg
SYMBOL res 304 736 R0
SYMATTR InstName R13
SYMATTR Value 68k
SYMBOL res 544 736 R0
SYMATTR InstName R14
SYMATTR Value 68k
SYMBOL res 752 736 M0
SYMATTR InstName R15
SYMATTR Value 68k
SYMBOL res 1136 736 R0
SYMATTR InstName R16
SYMATTR Value 68k
SYMBOL OpAmps\\opamp 800 528 R90
SYMATTR InstName U1
SYMATTR SpiceLine Aol=5Meg
SYMATTR SpiceLine2 GBW=60Meg
TEXT -408 40 Left 2 !.ic v(vp3)=5 V(VG)=-6.8
TEXT -408 72 Left 2 !.tran 0 10 0 1u uic
TEXT -408 8 Left 2 !.options plotwinsize=0 numdgt=7
TEXT -408 104 Left 2 !.lib opamp.sub
TEXT -408 136 Left 2 !.ic v(vout)=2 v(vx)=-4
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnn0gk$i856$1@dont-email.me...
On 2/02/2025 3:05 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnmpgh$dafg$1@dont-email.me...
On 2/02/2025 4:26 am, Edward Rawde wrote:...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?
I'll pass.
If your circuit design skills are demonstrated by a circuit which uses 93 components (which includes 9 transistors and 10
integrated
circuits) and only gets 60dB down on harmonics then I agree that pass is for the best.
If you think that circuit design skills can be assessed by counting components, we can draw our own conclusions.
Stop making me laugh please Bill.
Who is "we" anyway. You sound like you speak for everyone here.
Approaching 130dB now. Any suggestions for improvement?
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
On Sun, 02 Feb 2025 01:02:22 +0000, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Sat, 1 Feb 2025 12:26:28 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...You aren't a quick study.
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...I've modified the circuit to make sure that FET gate doesn't get forward-biased.
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else. >>>>>>>>>
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the
source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and
I'm
not interested enough to try and work how it is actually working. >>>>>>
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
Did he say why?
I've swapped in a J111. The integrator around U6
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot
of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Sorry bill but I don't get why you would sabotage the circuit like that. >>>>
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at all.
Perhaps if you measure the distortion only when the stabilisation circuit isn't feeding anything into the integrator wrapped
around U6.
The current feed to set the output level by balancing out the inputs from the rectifiers was feeding in current when it should
have been sucking it out, so it wasn't a well thought-out design.
Here's a version of that circuit which does work sensibly, even if the harmonic content of the output is only about 60DB below
the fundamental.
But that's completely nuts Bill.
And so is Bill! Sadly, Bill stopped making useful contributions to
this group many years ago and now spends his days attempting to appear superior to everyone else.
If I really do want 1kHz with -133dB harmonic distortion in reality then I'm prepared to wait 20 seconds for it.
In fact I'm prepared to wait a minute or two if that's what it takes for the harmonic distortion to go down to -133dB.
Of course. Nothing unreasonable about that.
If there's a problem with the design around U6 then why doesn't that also apply to U7 and U9?
It's not intended as a volume production design. I might make two or three boards and test it.
But I don't have equipment capable of measuring -133dB harmonic distortion. >>>
I would also be prepared to make adjustments to the circuit for minimum distortion.
This circuit might have up to six adjustments if built for real so it can be adjusted for correct output level and minimum
distortion.
The circuit included below might be my final offering on this matter.
There's nothing visible at 2kHz and 3kHz is barely visible.
It requires only a cheap quad op amp package in addition to the two LT1115 devices.
If you can show me a circuit which has -133dB harmonic distortion and also faster settling time then I'd like to see it but if
you're going to insist that it has to have only -60 dB harmonic distortion performance (which interestingly is about that of your
own circuit) just because the settling time can be made shorter then I'm sorry but all that's going to do is make me wonder about
your mental health.
Many of us here have been wondering about Bill's mental health for the
past 2 decades. Please try to remember you're dealing with SED's
biggest troll here (and he hasn't been fed well lately).
On 2/02/2025 8:23 pm, Cursitor Doom wrote:
On Sun, 02 Feb 2025 01:02:22 +0000, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Sat, 1 Feb 2025 12:26:28 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...You aren't a quick study.
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...I've modified the circuit to make sure that FET gate doesn't get forward-biased.
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the
source or
drain, it acts as a diode and feeds current into the channel. >>>>>>>>>
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the
source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator,
and
I'm
not interested enough to try and work how it is actually working. >>>>>>>
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
Did he say why?
I've swapped in a J111. The integrator around U6
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a
lot
of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Sorry bill but I don't get why you would sabotage the circuit like that. >>>>>
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback
control
problem which you seem to be reluctant to recognise.
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at
all.
Perhaps if you measure the distortion only when the stabilisation circuit isn't feeding anything into the integrator wrapped
around U6.
The current feed to set the output level by balancing out the inputs from the rectifiers was feeding in current when it
should
have been sucking it out, so it wasn't a well thought-out design.
Here's a version of that circuit which does work sensibly, even if the harmonic content of the output is only about 60DB
below
the fundamental.
But that's completely nuts Bill.
And so is Bill! Sadly, Bill stopped making useful contributions to
this group many years ago and now spends his days attempting to appear
superior to everyone else.
If I really do want 1kHz with -133dB harmonic distortion in reality then I'm prepared to wait 20 seconds for it.
In fact I'm prepared to wait a minute or two if that's what it takes for the harmonic distortion to go down to -133dB.
Of course. Nothing unreasonable about that.
If there's a problem with the design around U6 then why doesn't that also apply to U7 and U9?
It's not intended as a volume production design. I might make two or three boards and test it.
But I don't have equipment capable of measuring -133dB harmonic distortion.
I would also be prepared to make adjustments to the circuit for minimum distortion.
This circuit might have up to six adjustments if built for real so it can be adjusted for correct output level and minimum
distortion.
The circuit included below might be my final offering on this matter.
There's nothing visible at 2kHz and 3kHz is barely visible.
It requires only a cheap quad op amp package in addition to the two LT1115 devices.
If you can show me a circuit which has -133dB harmonic distortion and also faster settling time then I'd like to see it but if
you're going to insist that it has to have only -60 dB harmonic distortion performance (which interestingly is about that of
your
own circuit) just because the settling time can be made shorter then I'm sorry but all that's going to do is make me wonder
about
your mental health.
I didn't insist on anything. I debugged Edward's simulation to the point where it started up properly
and settled down to a stable state fairly quickly, and reported that the changes that I'd made had upped the harmonic content.
After I'd found another bug in his design I finally got the harmonic content closer to about 75dB below the fundamental.
My current mirror variation is stuck at a -60dB. Posting it here didn't get me any helpful suggestions about making it better.
Many of us here have been wondering about Bill's mental health for the
past 2 decades. Please try to remember you're dealing with SED's
biggest troll here (and he hasn't been fed well lately).
Cursitor Doom - who actually is an anonymous troll - does like to claim that people who object to his habit of posting fatuous
nonsense aren't to be taken seriously. One can understand why - it's just one more tranche of fatuous nonsense, and he gets some
kind of bizarre satisfaction from posting all sorts of different kinds of utter nonsense.
I really shouldn't go to the trouble of objecting one more example of his malicious fantasising, but I do find it irritating when
he starts sticking his oar into serious discussions.
--
Bill Sloman, Sydney
On Thu, 30 Jan 2025 13:47:31 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
Approaching 130dB now. Any suggestions for improvement?
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
If you actually build one, how would you measure the distortion?
(I can think of one way)
I'd expect it to be worse than the sim, even ignoring noise.
There is a hobby of playing with LT Spice as a sort of video game,
never building or even needing the circuit. Nothing wrong with that I
guess, except that the pay isn't very good.
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vno724$oica$1@dont-email.me...
On 2/02/2025 8:23 pm, Cursitor Doom wrote:
On Sun, 02 Feb 2025 01:02:22 +0000, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Sat, 1 Feb 2025 12:26:28 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...I've modified the circuit to make sure that FET gate doesn't get forward-biased.
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the
source or
drain, it acts as a diode and feeds current into the channel. >>>>>>>>>>
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the
source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator,
and
I'm
not interested enough to try and work how it is actually working. >>>>>>>>
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
Did he say why?
I've swapped in a J111. The integrator around U6
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a
lot
of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Sorry bill but I don't get why you would sabotage the circuit like that.
You aren't a quick study.
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback
control
problem which you seem to be reluctant to recognise.
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at
all.
Perhaps if you measure the distortion only when the stabilisation circuit isn't feeding anything into the integrator wrapped
around U6.
The current feed to set the output level by balancing out the inputs from the rectifiers was feeding in current when it
should
have been sucking it out, so it wasn't a well thought-out design.
Here's a version of that circuit which does work sensibly, even if the harmonic content of the output is only about 60DB
below
the fundamental.
But that's completely nuts Bill.
And so is Bill! Sadly, Bill stopped making useful contributions to
this group many years ago and now spends his days attempting to appear
superior to everyone else.
If I really do want 1kHz with -133dB harmonic distortion in reality then I'm prepared to wait 20 seconds for it.
In fact I'm prepared to wait a minute or two if that's what it takes for the harmonic distortion to go down to -133dB.
Of course. Nothing unreasonable about that.
If there's a problem with the design around U6 then why doesn't that also apply to U7 and U9?
It's not intended as a volume production design. I might make two or three boards and test it.
But I don't have equipment capable of measuring -133dB harmonic distortion.
I would also be prepared to make adjustments to the circuit for minimum distortion.
This circuit might have up to six adjustments if built for real so it can be adjusted for correct output level and minimum
distortion.
The circuit included below might be my final offering on this matter. >>>>> There's nothing visible at 2kHz and 3kHz is barely visible.
It requires only a cheap quad op amp package in addition to the two LT1115 devices.
If you can show me a circuit which has -133dB harmonic distortion and also faster settling time then I'd like to see it but if
you're going to insist that it has to have only -60 dB harmonic distortion performance (which interestingly is about that of
your
own circuit) just because the settling time can be made shorter then I'm sorry but all that's going to do is make me wonder
about
your mental health.
I didn't insist on anything. I debugged Edward's simulation to the point where it started up properly
What is the difference between starting up properly and starting up the way the unmodified circuit starts up?
If I didn't have LTSpice and tested a real circuit then I'd likely never know what this circuit does in the time before I've even
got my fingers off the power switch.
And I have no reason to care if the gate-source voltage goes a few mv positive during startup.
and settled down to a stable state fairly quickly, and reported that the changes that I'd made had upped the harmonic content.
After I'd found another bug in his design I finally got the harmonic content closer to about 75dB below the fundamental.
I designed a new piano today. I found a bug in the sustain pedal mechanism and polished the cabinet to over 80pB.
I can't understand why no musician wants to play it.
My friend said he'd buy one if I can tune it properly but I can't understand why that matters. All the other parameters are perfect.
You can even open the lid in less than 20ms.
My current mirror variation is stuck at a -60dB. Posting it here didn't get me any helpful suggestions about making it better.
My piano design has 9 transistors per string and I haven't made even the slightest attempt to explain why this might lead to a
solution which is an improvement over using a FET.
I can't understand why no-one else cares but I have a PhD in string design so there must be something better about my piano when
compared with a piano produced by a designer who likes to try things out to see what works best as well as use PhD level theory when
it's needed.
Many of us here have been wondering about Bill's mental health for the
past 2 decades. Please try to remember you're dealing with SED's
biggest troll here (and he hasn't been fed well lately).
Cursitor Doom - who actually is an anonymous troll - does like to claim that people who object to his habit of posting fatuous
nonsense aren't to be taken seriously. One can understand why - it's just one more tranche of fatuous nonsense, and he gets some
kind of bizarre satisfaction from posting all sorts of different kinds of utter nonsense.
Yeah well some people's facts are other people's utter nonsense.
Just ask Donald Trump.
So I don't see the point of getting so worked up about human nature which isn't going to change any time soon.
I really shouldn't go to the trouble of objecting one more example of his malicious fantasising, but I do find it irritating when
he starts sticking his oar into serious discussions.
In that case I'd relax and just ignore anything which irritates you that much and which you can do nothing to change.
He does make me laugh sometimes (and so do you). The last example was something along the lines of aliens must be here because
unidentified objects have been seen in the sky.
But I don't get irritated by that, just amused.
There seem to be some people who think that the earth is flat or that it was once called teegeeack (at a time when there were no
people but let's not allow facts to distract us).
And nothing is going to change their mind. Attempting to persuade them that they are nuts will just reinforce their belief that it's
you who must be nuts.
If I let these things bother me (or worse, told the people who believe it that they were nuts) I'd never get anything done and it's
likely that plenty of people wouldn't like me very much and therefore they would not be inclined to offer me any help with my piano
(sorry current mirror) design.
On Sun, 2 Feb 2025 00:50:10 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnn0gk$i856$1@dont-email.me...
On 2/02/2025 3:05 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnmpgh$dafg$1@dont-email.me...
On 2/02/2025 4:26 am, Edward Rawde wrote:...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?
I'll pass.
If your circuit design skills are demonstrated by a circuit which uses 93 components (which includes 9 transistors and 10
integrated
circuits) and only gets 60dB down on harmonics then I agree that pass is for the best.
If you think that circuit design skills can be assessed by counting components, we can draw our own conclusions.
Stop making me laugh please Bill.
If you are unemployable and never build what you simulate, more parts
are no problem.
Who is "we" anyway. You sound like you speak for everyone here.
That's the Royal We.
On Thu, 30 Jan 2025 13:47:31 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
Approaching 130dB now. Any suggestions for improvement?
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
If you actually build one, how would you measure the distortion?
(I can think of one way).
I'd expect it to be worse than the sim, even ignoring noise.
There is a hobby of playing with LT Spice as a sort of video game,
never building or even needing the circuit.
Nothing wrong with that I guess, except that the pay isn't very good.
"john larkin" <JL@gct.com> wrote in message news:tk6vpjp7tn5hct35jo5ue4846p9vt8ggt1@4ax.com...
On Thu, 30 Jan 2025 13:47:31 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
Approaching 130dB now. Any suggestions for improvement?
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
If you actually build one, how would you measure the distortion?
(I can think of one way)
I'd probably ask you what you thought the best way of measuring it would be.
I'd expect it to be worse than the sim, even ignoring noise.
I would too.
There is a hobby of playing with LT Spice as a sort of video game,
never building or even needing the circuit. Nothing wrong with that I
guess, except that the pay isn't very good.
I wasn't expecting to get below -120dB in a simulation but the current circuit is approaching -140dB in a simulation.
I have definitely found it fun to do and also to improve it using suggestions from people here.
And I have learned a lot about how to use LTSpice which makes it much quicker and easier to simulate anything I might get paid for.
From a sinewave oscillator point of view the original objective was to find out whether it's really necessary (at least at one fixed
frequency) to use lamps, thermistors or opto devices to get the lowest possible distortion.
That question seems to have been answered.
On Sat, 1 Feb 2025 12:26:28 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...
On 1/02/2025 4:37 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...You aren't a quick study.
On 1/02/2025 1:34 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...
On 31/01/2025 5:47 am, Edward Rawde wrote:
Approaching 130dB now. Any suggestions for improvement?But at least I know what mine are doing.
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.
This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else. >>>>>>>>
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.
This is a strange circuit.
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the
source
or
drain.
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and
I'm
not interested enough to try and work how it is actually working.
I've modified the circuit to make sure that FET gate doesn't get forward-biased.
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
As John May pointed out a long time ago, the J113 isn't a great choice for the application.
Did he say why?
I've swapped in a J111. The integrator around U6
isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot
of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.
Sorry bill but I don't get why you would sabotage the circuit like that. >>>
Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at all.
Perhaps if you measure the distortion only when the stabilisation circuit isn't feeding anything into the integrator wrapped
around U6.
The current feed to set the output level by balancing out the inputs from the rectifiers was feeding in current when it should
have been sucking it out, so it wasn't a well thought-out design.
Here's a version of that circuit which does work sensibly, even if the harmonic content of the output is only about 60DB below
the fundamental.
But that's completely nuts Bill.
If I really do want 1kHz with -133dB harmonic distortion in reality then I'm prepared to wait 20 seconds for it.
In fact I'm prepared to wait a minute or two if that's what it takes for the harmonic distortion to go down to -133dB.
If there's a problem with the design around U6 then why doesn't that also apply to U7 and U9?
It's not intended as a volume production design. I might make two or three boards and test it.
But I don't have equipment capable of measuring -133dB harmonic distortion. >>
I would also be prepared to make adjustments to the circuit for minimum distortion.
This circuit might have up to six adjustments if built for real so it can be adjusted for correct output level and minimum
distortion.
The circuit included below might be my final offering on this matter.
There's nothing visible at 2kHz and 3kHz is barely visible.
It requires only a cheap quad op amp package in addition to the two LT1115 devices.
If you can show me a circuit which has -133dB harmonic distortion and also faster settling time then I'd like to see it but if
you're going to insist that it has to have only -60 dB harmonic distortion performance (which interestingly is about that of your
own circuit) just because the settling time can be made shorter then I'm sorry but all that's going to do is make me wonder about
your mental health.
If you believe that a real version of the circuit below could not be adjusted to better than -130dB (with suitable test equipment)
then please let me know.
It might take an hour to complete the adjustments but that's ok with me because as previously stated it's not intended as a
production design which just works after assembly.
It takes my computer about 10 minutes (LTSpice 24.1.1) to complete 20 seconds of simulation for the following circuit.
I usually watch the output and the current in each of the four diodes.
When it's done, take a sample of the output near 20s and FFT with Blackman-Harris window.
I you're using polyphase sampling you may as well use a svo. The
LT115 is not a good choice - it's phase margin is close to zero and it
is liable to sing at about 25MHz.
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